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PIC18F23K20-E/ML Datasheet(PDF) 409 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 409 Page - Microchip Technology |
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409 / 420 page  © 2007 Microchip Technology Inc. Advance Information DS41303B-page 407 PIC18F2XK20/4XK20 CONFIG7H Register ........................................................ 290 CONFIG7L Register ......................................................... 290 Configuration Bits ............................................................. 284 Configuration Register Protection .................................... 297 Context Saving During Interrupts ..................................... 113 CPFSEQ .......................................................................... 316 CPFSGT .......................................................................... 317 CPFSLT ........................................................................... 317 Customer Change Notification Service ............................ 409 Customer Notification Service .......................................... 409 Customer Support ............................................................ 409 CVREF Voltage Reference Specifications ........................ 365 D Data Addressing Modes ..................................................... 80 Comparing Addressing Modes with the Extended Instruction Set Enabled ..................... 83 Direct .......................................................................... 80 Indexed Literal Offset ................................................. 82 Instructions Affected .......................................... 82 Indirect ....................................................................... 80 Inherent and Literal .................................................... 80 Data EEPROM Code Protection ....................................................... 297 Data EEPROM Memory ..................................................... 95 Associated Registers ................................................. 98 EEADR Register ........................................................ 95 EECON1 and EECON2 Registers ............................. 95 Operation During Code-Protect ................................. 98 Protection Against Spurious Write ............................. 98 Reading ...................................................................... 97 Using .......................................................................... 98 Write Verify ................................................................ 97 Writing ........................................................................ 97 Data Memory ..................................................................... 69 Access Bank .............................................................. 74 and the Extended Instruction Set ............................... 82 Bank Select Register (BSR) ....................................... 69 General Purpose Registers ........................................ 74 Map for PIC18F23K20/43K20 .................................... 70 Map for PIC18F24K20/44K20 .................................... 71 Map for PIC18F25K20/45K20 .................................... 72 Special Function Registers ........................................ 74 DAW ................................................................................. 318 DC and AC Characteristics Graphs and Tables .................................................. 387 DC Characteristics Input/Output ............................................................. 362 Peripheral Supply Current ........................................ 361 Power-Down Current ............................................... 355 Primary Idle Supply Current ..................................... 359 Primary Run Supply Current .................................... 358 RC Idle Supply Current ............................................ 357 RC Run Supply Current ........................................... 356 Secondary Oscillator Supply Current ....................... 360 Supply Voltage ......................................................... 355 DCFSNZ .......................................................................... 319 DECF ............................................................................... 318 DECFSZ ........................................................................... 319 Development Support ...................................................... 349 Device Differences ........................................................... 397 Device Overview .................................................................. 9 Details on Individual Family Members ....................... 10 Features (table) .......................................................... 11 New Core Features ...................................................... 9 Other Special Features .............................................. 10 Device Reset Timers ......................................................... 53 Oscillator Start-up Timer (OST) ................................. 53 PLL Lock Time-out .................................................... 53 Power-up Timer (PWRT) ........................................... 53 Time-out Sequence ................................................... 53 DEVID1 Register ............................................................. 291 DEVID2 Register ............................................................. 291 Direct Addressing .............................................................. 81 E ECCPAS Register ............................................................ 173 EECON1 Register ........................................................ 87, 96 Effect on Standard PIC Instructions ................................. 346 Effects of Power Managed Modes on Various Clock Sources ........................................................... 34 Effects of Reset PWM mode .............................................................. 160 Electrical Characteristics ................................................. 353 Enhanced Capture/Compare/PWM (ECCP) .................... 163 Associated Registers ............................................... 181 Capture and Compare Modes ................................. 164 Capture Mode. See Capture (ECCP Module). Enhanced PWM Mode ............................................. 165 Auto-Restart .................................................... 174 Auto-shutdown ................................................ 173 Direction Change in Full-Bridge Output Mode . 171 Full-Bridge Application ..................................... 169 Full-Bridge Mode ............................................. 169 Half-Bridge Application .................................... 168 Half-Bridge Application Examples ................... 175 Half-Bridge Mode ............................................. 168 Output Relationships (Active-High and Active-Low) .............................................. 166 Output Relationships Diagram ......................... 167 Programmable Dead Band Delay .................... 175 Shoot-through Current ..................................... 175 Start-up Considerations ................................... 172 Outputs and Configuration ....................................... 164 Standard PWM Mode .............................................. 164 Timer Resources ..................................................... 164 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................. 223 Errata ................................................................................... 8 EUSART .......................................................................... 223 Asynchronous Mode ................................................ 225 12-bit Break Transmit and Receive ................. 241 Associated Registers, Receive ........................ 231 Associated Registers, Transmit ....................... 227 Auto-Wake-up on Break .................................. 240 Baud Rate Generator (BRG) ........................... 235 Clock Accuracy ................................................ 232 Receiver .......................................................... 228 Setting up 9-bit Mode with Address Detect ..... 230 Transmitter ...................................................... 225 Baud Rate Generator (BRG) Associated Registers ....................................... 235 Auto Baud Rate Detect .................................... 239 Baud Rate Error, Calculating ........................... 235 Baud Rates, Asynchronous Modes ................. 236 Formulas .......................................................... 235 High Baud Rate Select (BRGH Bit) ................. 235 Clock polarity Synchronous Mode .......................................... 243 Data polarity Asychronous Receive ...................................... 228 Asychronous Transmit ..................................... 225 |
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