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PIC18F23K20-E/ML Datasheet(PDF) 415 Page - Microchip Technology |
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PIC18F23K20-E/ML Datasheet(HTML) 415 Page - Microchip Technology |
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415 / 420 page  © 2007 Microchip Technology Inc. Advance Information DS41303B-page 413 PIC18F2XK20/4XK20 Timer1 .............................................................................. 139 16-Bit Read/Write Mode ........................................... 141 Associated Registers ............................................... 144 Interrupt .................................................................... 142 Operation ................................................................. 140 Oscillator .......................................................... 139, 141 Oscillator Layout Considerations ............................. 142 Overflow Interrupt .................................................... 139 Resetting, Using the CCP Special Event Trigger ..... 142 Special Event Trigger (ECCP) ................................. 164 TMR1H Register ...................................................... 139 TMR1L Register ....................................................... 139 Use as a Real-Time Clock ....................................... 143 Timer2 .............................................................................. 145 Associated Registers ............................................... 146 Interrupt .................................................................... 146 Operation ................................................................. 145 Output ...................................................................... 146 Timer3 .............................................................................. 147 16-Bit Read/Write Mode ........................................... 149 Associated Registers ............................................... 150 Operation ................................................................. 148 Oscillator .......................................................... 147, 149 Overflow Interrupt ............................................ 147, 149 Special Event Trigger (CCP) .................................... 150 TMR3H Register ...................................................... 147 TMR3L Register ....................................................... 147 Timing Diagrams A/D Conversion ........................................................ 385 Acknowledge Sequence .......................................... 217 Asynchronous Reception ......................................... 230 Asynchronous Transmission .................................... 226 Asynchronous Transmission (Back to Back) ........... 227 Auto Wake-up Bit (WUE) During Normal Operation 240 Auto Wake-up Bit (WUE) During Sleep ................... 241 Automatic Baud Rate Calculator .............................. 239 Baud Rate Generator with Clock Arbitration ............ 211 BRG Reset Due to SDA Arbitration During Start Condition ................................................. 220 Brown-out Reset (BOR) ........................................... 372 Bus Collision During a Repeated Start Condition (Case 1) ........................................... 221 Bus Collision During a Repeated Start Condition (Case 2) ........................................... 221 Bus Collision During a Start Condition (SCL = 0) .... 220 Bus Collision During a Stop Condition (Case 1) ...... 222 Bus Collision During a Stop Condition (Case 2) ...... 222 Bus Collision During Start Condition (SDA only) ..... 219 Bus Collision for Transmit and Acknowledge ........... 218 Capture/Compare/PWM (CCP) ................................ 373 CLKO and I/O .......................................................... 370 Clock Synchronization ............................................. 204 Clock/Instruction Cycle .............................................. 67 Comparator Output .................................................. 263 Example SPI Master Mode (CKE = 0) ..................... 375 Example SPI Master Mode (CKE = 1) ..................... 376 Example SPI Slave Mode (CKE = 0) ....................... 377 Example SPI Slave Mode (CKE = 1) ....................... 378 External Clock (All Modes except PLL) .................... 369 Fail-Safe Clock Monitor (FSCM) ................................ 39 First Start Bit Timing ................................................ 212 Full-Bridge PWM Output .......................................... 170 Half-Bridge PWM Output ................................. 168, 175 High/Low-Voltage Detect Characteristics ................ 366 High/Low-Voltage Detect Operation (VDIRMAG = 0) ............................................... 279 High/Low-Voltage Detect Operation (VDIRMAG = 1) ............................................... 280 I2C Bus Data ............................................................ 379 I2C Bus Start/Stop Bits ............................................ 379 I2C Master Mode (7 or 10-Bit Transmission) ........... 215 I2C Master Mode (7-Bit Reception) ......................... 216 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 200 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 206 I2C Slave Mode (10-Bit Transmission) .................... 201 I2C Slave Mode (7-bit Reception, SEN = 0) ............ 198 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 205 I2C Slave Mode (7-Bit Transmission) ...................... 199 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............ 207 I2C Stop Condition Receive or Transmit Mode ........ 217 Internal Oscillator Switch Timing ............................... 37 Master SSP I2C Bus Data ....................................... 381 Master SSP I2C Bus Start/Stop Bits ........................ 381 Parallel Slave Port (PIC18F4XK20) ......................... 374 Parallel Slave Port (PSP) Read ............................... 134 Parallel Slave Port (PSP) Write ............................... 134 PWM Auto-shutdown Auto-restart Enabled ........................................ 174 Firmware Restart ............................................. 174 PWM Direction Change ........................................... 171 PWM Direction Change at Near 100% Duty Cycle .. 172 PWM Output (Active-High) ...................................... 166 PWM Output (Active-Low) ....................................... 167 Repeat Start Condition ............................................ 213 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST), Power-up Timer (PWRT) ........... 371 Send Break Character Sequence ............................ 242 Slave Synchronization ............................................. 189 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 55 SPI Mode (Master Mode) ........................................ 188 SPI Mode (Slave Mode, CKE = 0) ........................... 190 SPI Mode (Slave Mode, CKE = 1) ........................... 190 Synchronous Reception (Master Mode, SREN) ...... 246 Synchronous Transmission ..................................... 244 Synchronous Transmission (Through TXEN) .......... 244 Time-out Sequence on POR w/PLL Enabled (MCLR Tied to VDD) .......................................... 55 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 1) ................................... 54 Time-out Sequence on Power-up (MCLR Not Tied to VDD, Case 2) ................................... 54 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ....................... 54 Timer0 and Timer1 External Clock .......................... 372 Transition for Entry to Sleep Mode ............................ 44 Transition for Wake from Sleep (HSPLL) .................. 44 Transition Timing for Entry to Idle Mode .................... 45 Transition Timing for Wake from Idle to Run Mode ... 45 USART Synchronous Receive (Master/Slave) ........ 383 USART Synchronous Transmission (Master/Slave) 383 Timing Diagrams and Specifications ............................... 369 A/D Conversion Requirements ................................ 385 Capture/Compare/PWM Requirements ................... 374 CLKO and I/O Requirements ................................... 371 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 375 (Master Mode, CKE = 1) .................................. 376 |
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