PIC24HJ32GP202-ESLASHML datasheet(49/244 Pages) MICROCHIP

49 / 244 page

Preliminary

DS70289A-page 47

PIC24HJ32GP202/204 and PIC24HJ16GP304

5.0

RESETS

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

• POR: Power-on Reset

• BOR: Brown-out Reset

•MCLR: Master Clear Pin Reset

•SWR: RESET Instruction

• WDTO: Watchdog Timer Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Opcode, Uninitialized W Regis-

ter Reset, and Security Reset

• CM: Configuration Mismatch Reset

Figure 5-1 shows the simplified block diagram of the

Reset module.

Any active source of Reset makes the SYSRST signal

active. Many registers associated with the CPU and

peripherals are forced to a known Reset state. Most

registers are unaffected by a Reset; their status is

unknown on POR and unchanged by all other Resets.

All types of device Reset will set a corresponding status

bit in the RCON register to indicate the type of Reset

(see Register 5-1). A POR will clear all bits, except for

the POR bit (RCON<0>), that are set. The user appli-

cation can set or clear any bit at any time during code

execution. The RCON bits only serve as status bits.

Setting a particular Reset status bit in software does

not cause a device Reset to occur.

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

FIGURE 5-1:

RESET SYSTEM BLOCK DIAGRAM

Note:

This data sheet summarizes the features

the

PIC24HJ32GP202/204

and

PIC24HJ16GP304 devices. It is not

intended to be a comprehensive reference

source. To complement the information in

this data sheet, refer to the “PIC24H

Family Reference Manual”.

Note:

Refer to the specific peripheral or CPU

section of this manual for register Reset

states.

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

MCLR

VDD

Internal

Regulator

BOR

Sleep or Idle

RESET Instruction

WDT

Module

Glitch Filter

Trap Conflict

Illegal Opcode

Uninitialized W Register

SYSRST

VDD Rise

Detect

POR

Configuration Mismatch

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