PIC18F258-ESLASHLSQTP datasheet(314/402 Pages) MICROCHIP

314 / 402 page

PIC18FXX8

DS41159E-page 312

RETFIE

Return from Interrupt

Syntax:

[

label ]

RETFIE [s]

Operands:

∈ [0,1]

Operation:

(TOS)

→ PC,

→ GIE/GIEH or PEIE/GIEL,

if s = 1

(WS)

→ W,

(STATUSS)

→ Status,

(BSRS)

→ BSR,

PCLATU, PCLATH are unchanged.

Status Affected:

GIE/GIEH, PEIE/GIEL.

Encoding:

0000

0001

000s

Description:

Return from interrupt. Stack is popped

and Top-of-Stack (TOS) is loaded into

the PC. Interrupts are enabled by

setting either the high or low priority

global interrupt enable bit. If ‘s’ = 1, the

contents of the shadow registers WS,

STATUSS and BSRS are loaded into

their corresponding registers W, Status

and BSR. If ‘s’ = 0, no update of these

registers occurs (default).

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Pop PC from

stack

Set GIEH or

GIEL

operation

Example:

RETFIE 1

After Interrupt

TOS

BSR

BSRS

Status

STATUSS

GIE/GIEH, PEIE/GIEL

RETLW

Return Literal to W

Syntax:

[

label ]

RETLW k

Operands:

≤ k ≤ 255

Operation:

→ W,

(TOS)

→ PC,

PCLATU, PCLATH are unchanged

Status Affected:

None

Encoding:

0000

1100

kkkk

Description:

W is loaded with the eight-bit literal ‘k’.

The program counter is loaded from the

top of the stack (the return address).

The high address latch (PCLATH)

remains unchanged.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

literal ‘k’

Process

Data

Pop PC

from stack,

Write to W

operation

Example:

CALL TABLE ; W contains table

; offset value

; W now has

; table value

TABLE

ADDWF PCL

; W = offset

RETLW k0

; Begin table

RETLW k1

;

RETLW kn

; End of table

Before Instruction

0x07

After Instruction

value of kn

PIC18F258-E/LSQTP Datasheet(PDF) 314 Page - Microchip Technology

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