PIC18F258-ESLASHLSQTP datasheet(397/402 Pages) MICROCHIP

397 / 402 page

DS41159E-page 395

PIC18FXX8

Timer1 ............................................................................... 113

16-bit Read/Write Mode ............................................ 115

Associated Registers ................................................ 116

Operation .................................................................. 114

Oscillator ........................................................... 113, 115

Overflow Interrupt ............................................. 113, 115

Special Event Trigger (CCP)............................. 115, 126

Special Event Trigger (ECCP) .................................. 133

TMR1H Register ....................................................... 113

TMR1L Register........................................................ 113

TMR3L Register........................................................ 119

Timer2 ............................................................................... 117

Associated Registers ................................................ 118

Operation .................................................................. 117

Postscaler.

See Postscaler, Timer2.

PR2 Register..................................................... 117, 128

Prescaler.

See Prescaler, Timer2.

SSP Clock Shift................................................. 117, 118

TMR2 Register.......................................................... 117

TMR2 to PR2 Match Interrupt ................... 117, 118, 128

Timer3 ............................................................................... 119

Associated Registers ................................................ 121

Operation .................................................................. 120

Oscillator ................................................................... 121

Overflow Interrupt ............................................. 119, 121

Special Event Trigger (CCP)..................................... 121

TMR3H Register ....................................................... 119

Timing Conditions ............................................................. 342

Load Conditions for Device

Timing Specifications ........................................ 342

Temperature and Voltage

Specifications – AC........................................... 342

Timing Diagrams

A/D Conversion ......................................................... 359

Acknowledge Sequence ........................................... 176

Baud Rate Generator with

Clock Arbitration ............................................... 170

BRG Reset Due to SDA Arbitration

During Start Condition ...................................... 179

Brown-out Reset (BOR) and

Low-Voltage Detect .......................................... 345

Bus Collision During a Repeated

Start Condition (Case 1) ................................... 180

Bus Collision During a Repeated

Start Condition (Case2) .................................... 180

Bus Collision During a Stop

Condition (Case 1) ............................................ 181

Bus Collision During a

Stop Condition (Case 2) ................................... 181

Bus Collision During

Start Condition (SCL = 0).................................. 179

Bus Collision During

Start Condition (SDA Only) ............................... 178

Bus Collision for Transmit and

Acknowledge .................................................... 177

Capture/Compare/PWM

(CCP1 and ECCP1) .......................................... 347

CLKO and I/O ........................................................... 344

Clock Synchronization .............................................. 163

Clock/Instruction Cycle ............................................... 41

External Clock........................................................... 343

First Start Bit ............................................................. 171

Full-Bridge PWM Output ........................................... 137

Half-Bridge PWM Output .......................................... 136

I2C Bus Data............................................................. 353

I2C Bus Start/Stop Bits ............................................. 353

I2C Master Mode (Reception,

7-bit Address) ................................................... 175

I2C Master Mode (Transmission,

7 or 10-bit Address) .......................................... 174

I2C Slave Mode (Transmission,

10-bit Address) ................................................. 161

I2C Slave Mode (Transmission,

7-bit Address) ................................................... 159

I2C Slave Mode with SEN = 0 (Reception,

10-bit Address) ................................................. 160

I2C Slave Mode with SEN = 0 (Reception,

7-bit Address) ................................................... 158

I2C Slave Mode with SEN = 1 (Reception,

10-bit Address) ................................................. 165

I2C Slave Mode with SEN = 1 (Reception,

7-bit Address) ................................................... 164

Low-Voltage Detect .................................................. 262

Master SSP I2C Bus Data ........................................ 355

Master SSP I2C Bus Start/Stop Bits ......................... 355

Parallel Slave Port (PIC18F248

and PIC18F458) ............................................... 348

Parallel Slave Port Read .......................................... 108

Parallel Slave Port Write........................................... 107

PWM Direction Change ............................................ 139

PWM Direction Change at Near

100% Duty Cycle .............................................. 139

PWM Output ............................................................. 128

Repeated Start Condition ......................................... 172

Reset, Watchdog Timer (WDT),

Oscillator Start-up Timer (OST),

Power-up Timer (PWRT) .................................. 345

Slave Mode General Call Address Sequence

(7 or 10-bit Address Mode)............................... 166

Slave Synchronization .............................................. 149

Slow Rise Time (MCLR Tied to VDD) ......................... 29

SPI Master Mode...................................................... 148

SPI Master Mode Example (CKE = 0) ...................... 349

SPI Master Mode Example (CKE = 1) ...................... 350

SPI Slave Mode (with CKE = 0)................................ 150

SPI Slave Mode (with CKE = 1)................................ 150

SPI Slave Mode Example (CKE = 0) ........................ 351

SPI Slave Mode Example (CKE = 1) ........................ 352

Stop Condition Receive or

Transmit Mode.................................................. 176

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) ........................................... 29

Time-out Sequence on Power-up

(MCLR Not Tied to VDD)

Case 1 ................................................................ 28

Case 2 ................................................................ 28

Time-out Sequence on Power-up

(MCLR Tied to VDD) ........................................... 28

Timer0 and Timer1 External Clock ........................... 346

Transition Between Timer1 and

OSC1 (HS with PLL)........................................... 22

Transition Between Timer1 and

OSC1 (HS, XT, LP) ............................................ 21

Transition Between Timer1 and

OSC1 (RC, EC) .................................................. 22

PIC18F258-E/LSQTP Datasheet(PDF) 397 Page - Microchip Technology

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