7

PI6C487016

Low Skew, 1-to-16

LVCMOS/LVTTL Clock Driver

PS8741D

07/29/05

Application Information

Wiring the differenctial input to accept single ended levels

Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of

R1 adn R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock

Figure 1: Single-ended Signal Driving Differential Input

Single Ended

Clock Input

R1

1K

R2

1K

C1

0.1µ

CLK1

nCLK1