UAA3522HL datasheet(21/28 Pages) PHILIPS

21 / 28 page

2000 Feb 18

Philips Semiconductors

Objective speciﬁcation

Low power dual-band GSM transceiver

with an image rejecting front-end

UAA3522HL

SERIAL TIMING CHARACTERISTICS

General conditions: VCC = 2.8 V; Tamb =25 °C; see Fig.6; unless otherwise speciﬁed.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

Serial programming clock (pin CLK)

rise time

−

fall time

−

Tcy(clk)

clock cycle time

100

−−

Enable programming (pin EN)

td(ENL-CLKH)

delay from enable active to rising clock edge

−−

td(CLKL-ENH)

delay from enable inactive to last falling clock edge

−−

tW(reg)(min)

minimum inactive pulse width when consecutively programming

two different registers

150

−−

tW(IFLO)(min)

minimum inactive pulse width when consecutively programming

two IF divider ratios

150

−−

tW(RFLO)(min)

minimum inactive pulse width when consecutively programming

two RF divider ratios

500

−−

tsu(ENH-CLKH)

enable set-up time to next rising clock edge

−−

tsu(DATA-CLK)

set-up time DATA to CLK

−−

th(DATA-CLK)

hold time DATA to CLK

−−

handbook, full pagewidth

FCA042

MSB

LSB

ACTIVE

INACTIVE

ADDRESS

td(ENL-CLKH)

td(CLKL-ENH)

tsu(ENH-CLKH)

tsu(DATA-CLK)

th(DATA-CLK)

Tcy(CLK)

CLK

DATA

Fig.6 Serial bus timing diagram.

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