PACE1757ME datasheet(26/34 Pages) PYRAMID

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PACE 1757 M/ME

Page 26 of 34

Document # MICRO-10 REV B

SIGNAL DESCRIPTIONS (Continued)

STATUS BUS

Mnemonic

Name

Description

AK0 - AK3

Access key

Active HIGH outputs corresponding to the AK field of the processor status

word used to match the Access Lock in the MMU for memory accesses

(a mismatch will cause the MMU to pull the

MEM PRT ER signal LOW),

and also indicate the processor state (PS). Priveledged instructions can

be executed with PS=0 only. These signals are tri-state for bus cycles not

assigned to this CPU

AS0 - AS3

Address state

Active HIGH outputs corresponding to the AS field of the processor status

word that selects the page register group in the MMU. In the DMA physical

demultiplexed mode, AS(0:1) will receive the 9th and 10th most significant

bits of the physical address for use in the BPU function. These signals are

tri-state in bus cycles not assigned to this CPU.

INFORMATION BUS

Mnemonic

Name

Description

IB0 - IB15

Information bus

A bi-directional time-multiplexed address/data BUS. IB0 is the most

significant bit.

EDC0-EDC5

Error Detection /

An active HIGH output BUS used for detection of errors on the data BUS

Correction Bus

(IB0-IB15) and correction of single errors. When working in parity mode

EDC0 is the parity bit. EDC1-EDC5 are undefined in this case.

A(0:1) /

Address Bus

An active HIGH output BUS from the PIC. Contains the address of the

EXT ADR(0:1)

current bus cycle as latched by the end of STRBA. In system configurations

A(2:15)

including the MMU function, the only active lines during memory cycles

are A(4:15). In this example, A(2:3) are high impedance (don't care) and

A(0:1) turn into inputs called Extended Addresses, EXT AD (0:1). In this

situation, these two lines, supplied by the MMU, will be used to operate the

programmable ready generation during bus cycles.

EXT ADR0 -

Extended Address

A bi-directionaly active HIGH BUS. In CPU cycles, it is an output BUS

EXT ADR7

Bus

that is used to select one of 256 pages, 4K words each, expanding the

direct addressing space to 1M word. In DMA cycles, indicated by DMA-

ACK being active, it is also an output BUS except when programmed for

the physical demultiplexed DMA mode. In this example, it becomes an

input to receive the eight most significant bits of the DMA physical address

for use in the BPU function.

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