MP6570GR datasheet(43/55 Pages) MPS

43 / 55 page

MP6570

– 3-PHASE BLDC CONTROLLER WITH HIGH-ACCURACY ANGULAR SENSOR

MP6570 Rev. 1.0

www.MonolithicPower.com

3/4/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Address: 3Bh

SLV_ADDR_SET

Slave Address

SLV_ADDR_SET

Slave Address

0 0000

12H

1 0000

52H

0 0001

13H

1 0001

53H

0 0010

18H

1 0010

58H

0 0011

19H

1 0011

59H

0 0100

1AH

1 0100

5AH

0 0101

1BH

1 0100

5BH

0 0110

1CH

1 0110

5CH

0 0111

1DH

1 0111

5DH

0 1000

1EH

1 1000

5EH

0 1001

1FH

1 1001

5FH

0 1010

20H

1 1010

60H

0 1011

21H

1 1011

61H

0 1100

22H

1 1100

62H

0 1101

23H

1 1101

63H

0 1110

24H

1 1110

64H

0 1111

25H

1 1111

65H

I2C Interface

If the COM_MOD[1:0] bits are set to 00, the I2C

interface is selected to write or read the register

values. The MP6570 uses standard I2C protocol

to write/read the RAM registers and non-volatile

memory.

Figure 31 details the various I2C protocols

supported by the MP6570. The supported

protocols include word write and word read.

The communication clock is supported with a

maximum frequency of 1000kHz.

slave address

(7-bit)

command code

(8-bit)

Data_H

(8-bit)

Data_L

(8-bit)

slave

address

(7-bit)

wr A

command code

(8-bit)

slave

address

(7-bit)

Rd A

Data_H

(8-bit)

Data_L

(8-bit)

start

stop

ACK

NA NACK

Master to

slave

Slave to

master

Write(bit value =

Rd Read(bit value =

Word Write:

Word Read:

Figure 31: I2C Read/Write Protocol

MP6570GR Datasheet(PDF) 43 Page - Monolithic Power Systems

MP6570GR Datasheet(HTML) 43 Page - Monolithic Power Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

Datasheet Download

Link URL