ICS839893I datasheet(7/10 Pages) ICST

7 / 10 page

Integrated

Circuit

Systems, Inc.

839893AYI

www.icst.com/products/hiperclocks.html

REV. A AUGUST 8, 2005

ICS839893I

LOW SKEW, 1-TO-13

LVCMOS/LVTTL BUFFER DIVIDER

OUTPUT ENABLE/DISABLE TIME

PERIOD

odc =

DDOX

x 100%

QA0:5,

QB0:5, QC

SCOPE

LVCMOS

SCOPE

LVCMOS

PARAMETER MEASUREMENT INFORMATION

OUTPUT SKEW

2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT

-1.25V±5%

VDD,

VDDO_A,

VDDO_B,VDDO_C

1.25V±5%

3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT

1.65V±5%

-1.65V±5%

PROPAGATION DELAY

OUTPUT RISE/FALL TIME

tsk(o)

DDOX

GND

VDD,

VDDO_A,

VDDO_B,VDDO_C

DDOX

QA0:QA5,

QB0:QB5,

CLK0,

CLK1

Clock

Outputs

20%

80%

20%

t F

1.25V

VOH - 0.15V

VOL

VOH

VOL

2.5V

tPHZ

tPZH

Output nDPx

(See Note)

(Low-level

enabling)

NOTE: The output is high except when disabled by the Sn control.

OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

BANK SKEW (where X denotes outputs in the same bank)

tsk(b)

DDOX

QX0:QX5

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