PM5357-BI datasheet(42/432 Pages) PMC

42 / 432 page

PRODUCTION

S/UNI-622-POS

PMC-Sierra, Inc.

PM5357

S/UNI-622-POS

DATASHEET

PMC-1980911

ISSUE 5

SATURN USER NETWORK INTERFACE (622-POS)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

9.4

Section and Line Status DCC Pins

Pin Name

Type

No.

Function

RSDCLK

Output

AB20

The receive section DCC clock (RSDCLK) is a

192 kHz clock used to update the RSD input.

RSDCLK is generated by gapping a 216 kHz clock.

RSD

Output

AC21

The receive section DCC (RSD) signal contains the

serial section data communications channel (D1, D2

D3) extracted from the incoming stream.

RSD is updated on the falling edge of RSDCLK.

RLDCLK

Output

Y19

The receive line DCC clock (RLDCLK) is a 576 kHz

clock used to update the RLD output. RLDCLK is

generated by gapping a 2.16 MHz clock.

RLD

Output

AA20

The receive line DCC (RLD) signal contains the serial

line data communications channel (D4 - D12)

extracted from the incoming stream.

RLD is updated on the falling edge of RLDCLK.

TSDCLK

Output

B20

The transmit section DCC clock (TSDCLK) is a

192 kHz clock used to sample the TSD input.

TSDCLK is generated by gapping a 216 kHz clock.

TSD

Input

C20

The transmit section DCC (TSD) signal contains the

serial section data communications channel (D1, D2

D3). When not used, this input should be connected

to logic zero.

TSD is sampled on the rising edge of TSDCLK.

TLDCLK

Output

C19

The transmit line DCC clock (TLDCLK) is a 576 kHz

clock used to sample the TLD input. TLDCLK is

generated by gapping a 2.16 MHz clock.

TLD

Input

D19

The transmit line DCC (TLD) signal contains the

serial line data communications channel (D4 - D12).

When not used, this input should be connected to

logic zero.

TLD is sampled on the rising edge of TLDCLK.

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