CY22395
CY22394
Document #: 38-07186 Rev. *C
Page 13 of 17
CY22393
3.3V Switching Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
1/t1
Output Frequency[4, 6]
Clock output limit, CMOS, Commercial
–
–
200
MHz
Clock output limit, CMOS, Industrial
–
–
166
MHz
Clock output limit, PECL, Commercial (CY22394
only)
100
–
400
MHz
Clock output limit, PECL, Industrial (CY22394
only)
125
–
375
MHz
t2
Output Duty Cycle[4, 7]
Duty cycle for outputs, defined as t2 ÷ t1,
Fout < 100 MHz, divider >= 2,
measured at VDD/2
45%
50%
55%
Duty cycle for outputs, defined as t2 ÷ t1,
Fout > 100 MHz or divider = 1,
measured at VDD/2
40%
50%
60%
t3
Rising Edge Slew Rate[4]
Output clock rise time, 20% to 80% of VDD
0.75
1.4
V/ns
t4
Falling Edge Slew Rate[4]
Output clock fall time, 20% to 80% of VDD
0.75
1.4
V/ns
t5
Output three-state Timing[4] Time for output to enter or leave three-state mode
after SHUTDOWN/OE switches
–
150
300
ns
t6
Clock Jitter[4, 8]
Peak-to-peak period jitter, CLK outputs
measured at VDD/2
–400
ps
v7
P+/P– Crossing Point[4]
Crossing point referenced to Vdd/2, balanced
resistor network (CY22394 only)
–0.2
0
0.2
V
t8
P+/P– Jitter[4, 8]
Peak-to-peak period jitter, P+/P– outputs
measured at crossing point (CY22394 only)
–200
ps
t9
Lock Time[4]
PLL Lock Time from Power-up
–
1.0
3
ms
2.5V Switching Characteristics (CY22395 only)[5]
Parameter
Description
Conditions
Min
Typ
Max
Unit
1/t1_2.5
Output Frequency[4, 6]
Clock output limit, LVCMOS
133
MHz
t2_2.5
Output Duty Cycle[4, 7]
Duty cycle for outputs, defined as t2 ÷ t1
measured at LVDD/2
40%
50%
60%
t3_2.5
Rising Edge Slew Rate[4]
Output clock rise time, 20% to 80% of LVDD
0.5
1.0
V/ns
t4_2.5
Falling Edge Slew Rate[4]
Output clock fall time, 20% to 80% of LVDD
0.5
1.0
V/ns
Notes
6. Guaranteed to meet 20%–80% output thresholds, duty cycle, and crossing point specifications.
7. Reference Output duty cycle depends on XTALIN duty cycle.
8. Jitter varies significantly with configuration. Reference Output jitter depends on XTALIN jitter and edge rate.
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