AM79C864A datasheet(21/51 Pages) AMD

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AMD

P R E L I M I N A R Y

3-23

Am79C864A

PLC-S Control Register C (PLC_CNTRL_C)

PLC_CNTRL_C has address OA (hex). It is readable

and writeable. Bits 1 through 15 are cleared with the as-

sertion of

RST. Bit 0 (CIPHER_ENABLE) assumes the

same value as SCRM after

RST is asserted.

The PLC_CNTRL_C register bit assignments are listed

in Table 4.

FOTOFF_

CTRL

RESERVED

SDOFF_

TIMER

SDOFF_

TIMER

SDON_

TIMER

SDON_

TIMER

FOTOFF_

CTRL

PLC_CNTRL_C

15535B-8

5432

CIPHER_

ENABLE

SDON_

ENABLE

SDOFF_

ENABLE

RESERVED

CIPHER_

LPBCK

Addr

(Hex)

Table 4. PLC_CNTRL_C

Bit

Name

Definition

15–14

RESERVED

These two bits are reserved for diagnostic purposes and must be 0 for normal operation.

13–12

SDOFF_TIMER

These two bits are used to select the timing values shown for deasserting Signal_Detect

ENABLE bit is set and scrambler/descrambler is enabled either (by SCRM or CIPHER_

ENABLE)

00=0.76

µs

01=1.32

µs

10=2.52

µs

11=5.12

µs

11–10

SDON_TIMER

These two bits are used to select the timing values shown for asserting Signal_Detect if SDON_

ENABLE bit is set and scrambler/descrambler is enabled either by hardware or software.

00=0.84

µs

01=1.32

µs

10=2.52

µs

11=5.12

µs

9–8

FOTOFF _CTRL

These two bits are used to control the assertion of FOTOFF signal of PLC-S if scrambler/

descrambler is enabled either (by SCRM or CIPHER_ENABLE). The following timing delays

are with respect to the time from which PLC-S output scrambled Quiet symbols on TDAT lines.

00=Timer is bypassed (i.e., FOTOFF is asserted at the same time when scrambled Quiet

symbols are output on TDAT lines)

01=30

µs delay

10=50

µs delay

11=FOTOFF is never asserted

SDON_ENABLE

If this bit is set and scrambler/descrambler is enabled (by SCRM or CIPHER_ENABLE), then

SDON_TIMER bits (11–10) will determine the delay for asserting the Signal_Detect signal.

During this time, the descrambler is allowed to acquire synchronization of its input stream.

SDOFF_ENABLE

If this bit is set and scrambler/descrambler is enabled (bySCRM or CIPHER_ENABLE ), then

SDOFF_TIMER bits (13–12) will determine the delay for deasserting the Signal_Detect signal.

5–2

RESERVED

Bits 5–2 are reserved and should be set to 0.

CIPHER_LPBCK

If this bit is set, then the output of the scrambler is looped back to the input of the

descrambler (within PLC-S).

CIPHER_ENABLE

This bit is used to enable and disable the scrambler/descrambler function if SCRM (pin #41)

is not asserted. If SCRM is asserted, this bit is automatically set to 1. If SCRM is not

asserted, the value of this bit is determined by software. The default state (SCRM not

asserted) is 0.

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