CYII4SC014KAA-GTC
CYII4SM014KAA-GEC
Document #: 38-05709 Rev. *B
Page 2 of 27
Architecture and Operation
Floor Plan
The basic architecture of the sensor is shown in Figure 1.
The Y shift registers point at a row of the imager array. This
row is selected and/or reset by the row drivers. There are 2 Y
shift registers: one points at the row that is read out and the
second one points at the row to be reset. The second pointer
may lead the first pointer by a specific number of rows. In that
case, the time difference between both pointers is the
integration time. Alternatively, both shift registers can point at
the same row for reset and readout for a faster reset
sequence. When the row is read out, it is also reset in order to
do double sampling for fixed pattern noise reduction.
The pixel array of the IBIS4-14000 consists of 4536 x 3024
active pixels and 24 additional columns and rows, which can
also be addressed (see Figure 2 on page 3). The column
amplifiers read out the pixel information and perform the
double sampling operation. They also multiplex the signals on
the readout buses, which are buffered by the output amplifiers.
The shift registers can be configured for various subsampling
modes. The output amplifiers can be individually powered
down. And some other extra functions are foreseen. These
options are configurable via a serial input port.
pixel array
4560 x 3048 active pixels
x-shift register
3048 column amplifiers
CLK_YR
SYNC_YR
4 parallel
analog
outputs
Pixel (0,0)
SHS
SHR
CLK_X
SYNC_X
CLK_YL
SYNC_YL
Figure 1. Block Diagram of the IBIS4-14000 Image Sensor
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