SC16C852LIB datasheet(29/60 Pages) PHILIPS

29 / 60 page

SC16C852L_2

Product data sheet

Rev. 02 — 25 January 2007

29 of 60

NXP Semiconductors

SC16C852L

1.8 V dual UART with 128-byte FIFOs and IrDA encoder/decoder

7.5 Line Control Register (LCR)

The Line Control Register is used to specify the asynchronous data communication

format. The word length, the number of stop bits, and the parity are selected by writing the

appropriate bits in this register.

Table 17.

Line Control Register bits description

Bit

Symbol

Description

LCR[7]

Divisor latch enable. The internal baud rate counter latch and Enhanced

Feature mode enable.

logic 0 = divisor latch disabled (normal default condition)

logic 1 = divisor latch enabled

LCR[6]

Set break. When enabled, the Break control bit causes a break condition to

be transmitted (the TX output is forced to a logic 0 state). This condition

exists until disabled by setting LCR[6] to a logic 0.

logic 0 = no TX break condition (normal default condition)

logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the

remote receiver to a line break condition

5:3

LCR[5:3]

Programs the parity conditions (see Table 18).

LCR[2]

Stop bits. The length of stop bit is speciﬁed by this bit in conjunction with the

programmed word length (see Table 19).

logic 0 or cleared = default condition

1:0

LCR[1:0]

Word length bits 1, 0. These two bits specify the word length to be

transmitted or received (see Table 20).

logic 0 or cleared = default condition

Table 18.

LCR[5:3] parity selection

LCR[5]

LCR[4]

LCR[3]

Parity selection

no parity

odd parity

even parity

forced parity ‘1’

forced parity ‘0’

Table 19.

LCR[2] stop bit length

LCR[2]

Word length (bits)

Stop bit length (bit times)

5, 6, 7, 8

⁄2

6, 7, 8

Table 20.

LCR[1:0] word length

LCR[1]

LCR[0]

Word length (bits)

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