Nexperia

PESD1V0R1BFSF

Extremely low capacitance bidirectional ESD protection diode

5. Pinning information

Table 2. Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1

K1

cathode (diode 1)

2

K2

cathode (diode 2)

Transparent

top view

2

1

DSN0603-2 (SOD962-2)

sym045

K2

K1

6. Ordering information

Table 3. Ordering information

Package

Type number

Name

Description

Version

PESD1V0R1BFSF

DSN0603-2

silicon, leadless ultra small package; 2 terminals; 0.4 mm

pitch; 0.6 mm x 0.3 mm x 0.3 mm body

SOD962-2

7. Application information

The device is designed for the protection of one bidirectional data line from surge pulses and ESD

damage. The device is suitable on lines where the signal polarities are both positive and negative

with respect to ground.

The device uses an advanced clamping structure showing a negative dynamic resistance.

This snap-back behavior strongly reduces the clamping voltage to the system behind the ESD

protection during an ESD event. Do not connect unlimited DC current sources to the data lines to

avoid keeping the ESD protection device in snap-back state after exceeding breakdown voltage

(due to an ESD pulse for instance).

aaa-002737

ESD protection diode

GND

line to be protected

Fig. 1. Application diagram

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge

transients. The following guidelines are recommended:

1. Place the device as close to the input terminal or connector as possible.

2. Minimize the path length between the device and the protected line.

3. Keep parallel signal paths to a minimum.

4. Avoid running protected conductors in parallel with unprotected conductors.

5. Minimize all Printed-Circuit Board (PCB) conductive loops including power and ground loops.

6. Minimize the length of the transient return path to ground.

7. Avoid using shared transient return paths to a common ground point.

8. Use ground planes whenever possible. For multilayer PCBs, use ground vias.

PESD1V0R1BFSF_SDS

All information provided in this document is subject to legal disclaimers.

©

Nexperia B.V. 2024. All rights reserved

Short data sheet

6 November 2024

2 / 7