TMS470PLF111 datasheet(49/63 Pages) TI

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TMS470PLF111

16/32-BIT RISC FLASH MICROCONTROLLER

SPNS113 – OCTOBER 2006

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

SPIn slave mode timing parameters

SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =

input, and SPInSOMI = output)(1)(2)(3)(4)(see Figure 19)

1 The MASTER bit is cleared and the CLOCK PHASE bit is cleared.

2 If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value.

3 For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.

4 tc(VCLK) = interface clock cycle time = 1/f(VCLK)

5 When the SPIn is in Slave mode, the following must be true:

For PS values from 1 to 255:tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 100 ns, where PS is the prescale value.

For PS values of 0:tc(SPC)S = 2tc(VCLK) ≥ 100 ns.

6 The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit.

MIN

MAX

UNIT

tc(SPC)S

Cycle time, SPInCLK(5)

100

256tc(VCLK)

2(6)

tw(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 0)

0.5tc(SPC)S – 0.25tc(VCLK)

0.5tc(SPC)S + 0.25tc(VCLK)

tw(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 1)

0.5tc(SPC)S – 0.25tc(VCLK) 0.5tc(SPC)S + 0.25tc(VCLK)

3(6)

tw(SPCL)S

Pulse duration, SPInCLK low (clock polarity = 0)

0.5tc(SPC)S – 0.25tc(VCLK)

0.5tc(SPC)S + 0.25tc(VCLK)

tw(SPCH)S

Pulse duration, SPInCLK high (clock polarity = 1)

0.5tc(SPC)S – 0.25tc(VCLK) 0.5tc(SPC)S + 0.25tc(VCLK)

4(6)

td(SPCH-SOMI)S

Delay time, SPInCLK high to SPInSOMI valid (clock

polarity = 0)

0.5tc(VCLK)

1.5tc(VCLK)

td(SPCL-SOMI)S

Delay time, SPInCLK low to SPInSOMI valid (clock

polarity = 1)

0.5tc(VCLK)

1.5tc(VCLK)

5(6)

tv(SPCH-SOMI)S

Valid time, SPInSOMI data valid after SPInCLK high

(clock polarity = 0)

tc(SPC)S–1.5tc(VCLK)-tf

tv(SPCL-SOMI)S

Valid time, SPInSOMI data valid after SPInCLK low (clock

polarity = 1)

tc(SPC)S–1.5tc(VCLK)-tr

6(6)

tsu(SIMO-SPCL)S

Setup time, SPInSIMO before SPInCLK low (clock

polarity = 0)

tsu(SIMO-SPCH)S

Setup time, SPInSIMO before SPInCLK high (clock

polarity = 1)

7(6)

tv(SPCL-SIMO)S

Valid time, SPInSIMO data valid after SPInCLK low (clock

polarity = 0)

tv(SPCH-SIMO)S

Valid time, SPInSIMO data valid after SPInCLK high

(clock polarity = 1)

TMS470PLF111 Datasheet(PDF) 49 Page - Texas Instruments

TMS470PLF111 Datasheet(HTML) 49 Page - Texas Instruments

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