PIC18F8722IPTQTP datasheet(99/448 Pages) MICROCHIP

99 / 448 page

 2004 Microchip Technology Inc.

Preliminary

DS39646B-page 97

PIC18F8722 FAMILY

7.0

EXTERNAL MEMORY BUS

The External Memory Bus allows the device to access

external memory devices (such as Flash, EPROM,

SRAM, etc.) as program or data memory. It supports

both 8-bit and 16-bit Data Width modes and four

address widths from 8 to 20 bits.

The bus is implemented with 28 pins, multiplexed

across four I/O ports. Three ports (PORTD, PORTE

and PORTH) are multiplexed with the address/data bus

for a total of 20 available lines, while PORTJ is

multiplexed with the bus control signals.

A list of the pins and their functions is provided in

Table 7-1.

TABLE 7-1:

PIC18F8527/8622/8627/8722 EXTERNAL BUS – I/O PORT FUNCTIONS

Note:

The external memory bus is not imple-

mented on PIC18F6527/6622/6627/6722

(64-pin) devices.

Name

Port

Bit

External Memory Bus Function

RD0/AD0

PORTD

Address bit 0 or Data bit 0

RD1/AD1

PORTD

Address bit 1 or Data bit 1

RD2/AD2

PORTD

Address bit 2 or Data bit 2

RD3/AD3

PORTD

Address bit 3 or Data bit 3

RD4/AD4

PORTD

Address bit 4 or Data bit 4

RD5/AD5

PORTD

Address bit 5 or Data bit 5

RD6/AD6

PORTD

Address bit 6 or Data bit 6

RD7/AD7

PORTD

Address bit 7 or Data bit 7

RE0/AD8

PORTE

Address bit 8 or Data bit 8

RE1/AD9

PORTE

Address bit 9 or Data bit 9

RE2/AD10

PORTE

Address bit 10 or Data bit 10

RE3/AD11

PORTE

Address bit 11 or Data bit 11

RE4/AD12

PORTE

Address bit 12 or Data bit 12

RE5/AD13

PORTE

Address bit 13 or Data bit 13

RE6/AD14

PORTE

Address bit 14 or Data bit 14

RE7/AD15

PORTE

Address bit 15 or Data bit 15

RH0/A16

PORTH

Address bit 16

RH1/A17

PORTH

Address bit 17

RH2/A18

PORTH

Address bit 18

RH3/A19

PORTH

Address bit 19

RJ0/ALE

PORTJ

Address Latch Enable (ALE) Control pin

RJ1/OE

PORTJ

Output Enable (OE) Control pin

RJ2/WRL

PORTJ

Write Low (WRL) Control pin

RJ3/WRH

PORTJ

Write High (WRH) Control pin

RJ4/BA0

PORTJ

Byte Address bit 0 (BA0)

RJ5/CE

PORTJ

Chip Enable (CE) Control pin

RJ6/LB

PORTJ

Lower Byte Enable (LB) Control pin

RJ7/UB

PORTJ

Upper Byte Enable (UB) Control pin

Note:

For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional

multiplexed features may be available on some pins.

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