PowerPC 405EXr

SPECIFIC AT IONS

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property of their respective holders. Copyright © 2007 Applied Micro Circuits Corporation. All Rights Reserved.

POWERPC405EXr_PB_v1.00_06_05_2007

Dual Bus Architecture

The 405EXr features two on-chip buses: a processor local bus (PLB) as

well as an on-chip peripheral bus (OPB). High speed peripheral, such as

PCI Express, DDR2 and the Security Engine connect directly to the 128-

bit, PLB4 bus up to 200MHz. Less demanding devices are connected to

the 32-bit OPB Bus up to 100MHz. An external peripheral controller

supports the NAND and NOR flash memory as well as slave peripheral

devices.

PowerPC Partners Ecosystem

AMCC's embedded PowerPC processors are supported by an extensive

ecosystem of products and services from a wide range of leading

suppliers. AMCC's PowerPC Partners program includes industry-

standard providers of:

• Embedded operating systems

• Hardware and software development tools

• Embedded software products and services

• Board-level products

• System design services

• Technical training.

For full details of the products and services available through the

PowerPC Partners program, or to browse support available for a specific

AMCC also provides an evaluation kit for this PowerPC processor,

including an optimized evaluation board, sample applications, and

other software.

Features

• Processor Speed (frequency): From 333 to 533MHz

• Performance: 1.52 DMIPs/MHz (810 DMIPS @ 533 MHz peak)

• Single 1-lane PCI Express port

• Supports up to 2 GBytes of DDR 1/2 DRAM

• High performance Security Engine (optional) supports IPSec, SSL,

DTLS and SRTP

• DMA Controller with four independent channels

• One 10/100/1000 Ethernet MAC with MAL DMA support

• 8/16/32-bit External Peripheral Bus Controller

• External Bus Master Interface (EBMI)

• 2 UARTs (one with full hardware modem flow control)

• 32 GPIOs

• NAND Flash Controller

• Universal Interrupt Controller: 10 external interrupts

• On-the-Go USB 2.0 port

• JTAG and realtime trace support in processor core

• RoHS compliant (lead-free) version available

Specifications

Technology

•

90nm CMOS Process

Performance (estimated)

• 506 Dhrystone 2.1 MIPS @ 333 MHz

• 810 Dhrystone 2.1 MIPS @ 533MHz

Frequency

• CPU: 533 MHz Maximum

• PLB: 200 MHz Maximum

• OPB: 100 MHz Maximum

• External Bus: 100 MHz Maximum

Power Dissipation

•1.5W typical

Case Temperature Range

• -40°C to + 85°C

Power Supply

• 1.2V (internal logic), 1.8V (DDR2), 2.5V (DDR1, Ethernet), 3.3V (1/0)

Packaging

• 388-pin E-PBGA 27mm

× 27mm (with 1mm ball pitch)