PPC440SP datasheet(10/85 Pages) AMCC

10 / 85 page

PowerPC 440SP Embedded Processor

AMCC Proprietary

Revision 1.23 - Sept 26, 2006

Data Sheet

– 32- and 64-byte burst transfers

– 166MHz, maximum 5.2GB/s (simultaneous read and write)

– Processor:Bus clock ratios of N:1 and N:2

•OPB

– Dynamic bus sizing: 32-, 16-, and 8-bit data path

– 32-bit address

– 83.33MHz, maximum 333MB/s

• DCR

– 32-bit data path

– 10-bit address

On-Chip SRAM/L2 Cache

Features include:

• Four banks of 64KB each for a total of 256KB

• Configurable as either L2 cache or SRAM

• Memory cycles supported:

– Single beat read and write, 1 to 16 bytes

– Quadword Read and Write burst for 12-bit master

– Guarded memory accesses on 4KB boundaries

• Sustainable 2.6GB/s peak bandwidth at 166MHz

• Use as an L2 cache improves processor performance and reduces the PLB load

– Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by

software

– Data Array and Tag Array parity

– Unified data and instruction cache

– Four-way set associative

– 36-bit addressing

– Full LRU replacement algorithm

– Write through, look aside

• Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet core

DDR PCI-X Interface

The DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local

memory. There are three separate interfaces supporting 32- and 64-bit PCI-X buses in DDR mode. All three

interfaces can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI

Version 2.3, is also supported.

Features include:

•PCI-X 2.0

– Split transactions

– Frequency to 266MHz

– 32- and 64-bit address/data bus

– ECC supported for 266MHz Mode 2 only

• PCI 2.3 backward compatibility

– Frequency to 66MHz

– 32- and 64-bit bus

• Can be the PCI Host Bus Bridge or an Adapter Device PCI interface

• Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can

be disabled for use with an external arbiter

• Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts

• Simple message passing capability

• Asynchronous to the PLB

PPC440SP Datasheet(PDF) 10 Page - Applied Micro Circuits Corporation

PPC440SP Datasheet(HTML) 10 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL