PPC440SPE-RNB533C datasheet(5/80 Pages) AMCC

5 / 80 page

PowerPC 440SPe Embedded Processor

Revision 1.23 - Sept 21, 2006

AMCC Proprietary

Preliminary Data Sheet

PPC440SPe Functional Block Diagram

Figure 2. PPC440SPe Functional Block Diagram

The PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus

™ Architecture.

Implemented with the Crossbar option, the CoreConnect buses provide:

• Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the

Read and Write data path (10.6 GB/s total)

• 32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/s

Processor Core

DCR Bus

32KB

On-chip Peripheral Bus (OPB)

GPIO

IIC

UART

Bridge

External

Clock,

Control,

Reset

Power

Mgmt

JTAG

Timers

MMU

OPB

Interrupt

Controller

Universal

I-Cache

32KB

D-Cache

XOR/DMA

PPC440

PCI-Express

MAL

Ethernet

DCRs

Timers

256 KB

Low Latency (LL) Segment

High Bandwidth (HB) Segment

Processor Local Bus (PLB)

Trace

Arb

PLB

I2O/DMA

Memory

PCI-E0 PCI-E1 PCI-E2

MII,

GMII

Queue

DDR PCI-X

4 lanes

8 lanes

4 lanes

IRQ Handler

PCI-E

Bus Controller

(EBC)

10/100/

1000

Controller

(DMA0 and

DMA1)

Accelerator

Unit

(DMA2)

Registers

64-bit

64+8

16 IRQs

DDR 1 and 2

SDRAM Cntl

L2 Cache/SRAM

MAC

PPC440SPE-RNB533C Datasheet(PDF) 5 Page - Applied Micro Circuits Corporation

PPC440SPE-RNB533C Datasheet(HTML) 5 Page - Applied Micro Circuits Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL