PPC440GP-3CC400CZ datasheet(52/83 Pages) AMCC

52 / 83 page

440GP – Power PC 440GP Embedded Processor

AMCC

Revision 1.07 – October 4, 2007

Data Sheet

UART1_RTS/DTR

UART1 Request To Send or Data Terminal Ready. The choice is

determined by a DCR register bit setting.

I/O

5V tolerant

3.3V LVTTL

1, 4

IIC Peripheral Interface

IIC0SClk

IIC0 Serial Clock.

I/O

5V tolerant

3.3V LVTTL

1, 2

IIC0SDA

IIC0 Serial Data.

I/O

5V tolerant

3.3V LVTTL

1, 2

IIC1SClk

IIC1 Serial Clock.

I/O

5V tolerant

3.3V LVTTL

1, 2

IIC1SDA

IIC1 Serial Data.

I/O

5V tolerant

3.3V LVTTL

1, 2

Interrupts Interface

IRQ00:10

External interrupt Requests 0 through 10.

5V tolerant

3.3V LVTTL

1, 5

IRQ11:12

External interrupt Requests 11 through 12.

3.3V PCI

JTAG Interface

TCK

Test Clock.

3.3V CMOS

w/pull-up

TDI

Test Data In.

3.3V CMOS

w/pull-up

TDO

Test Data Out.

3.3V LVTTL

TMS

Test Mode Select.

3.3V CMOS

w/pull-up

TRST

Test Reset. During chip power-up, this signal must be low from the

start of VDD ramp-up until at least 16 SysClk cycles after VDD is

stable in order to initialize the JTAG controller.

3.3V CMOS

w/pull-up

Signal Functional Description (Sheet 5 of 7)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to 3.3V, 10kΩ to 5V)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to 3.3V)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440GP-3CC400CZ Datasheet(PDF) 52 Page - Applied Micro Circuits Corporation

PPC440GP-3CC400CZ Datasheet(HTML) 52 Page - Applied Micro Circuits Corporation

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