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PPC440GR-3PBFFFCX Datasheet(PDF) 5 Page - Applied Micro Circuits Corporation |
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PPC440GR-3PBFFFCX Datasheet(HTML) 5 Page - Applied Micro Circuits Corporation |
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5 / 82 page  AMCC Proprietary 5 440GR – PPC440GR Embedded Processor Preliminary Data Sheet Revision 1.16 – July 19, 2006 Block Diagram Figure 2. PPC440GR Functional Block Diagram The PPC440GR is a system on a chip (SOC) using IBM CoreConnect Bus™ Architecture. Processor Core DCR Bus 32KB On-chip Peripheral Bus (OPB) GPIO IIC UART DMA Bridge PLB4 (128 bits) DDR SDRAM External Peripheral Controller Controller Clock Control Reset Power Mgmt JTAG Trace Timers MMU Controller OPB - 30-bit addr - 16-bit data - 13-bit addr - 32-bit data NAND Flash Controller I-Cache 32KB D-Cache PPC440 PCI Bridge x2 x4 MAL Ethernet x2 DCRs GPT 1 MII or 2 RMII or 2 SMII ZMII 66MHz max 10/100 66MHz max 266MHz max PLB3 (64 bits) PLB Bridge SPI - 32 bits - 6 devices Performance Monitor BSC DMA Controller UIC External 10 Interrupts |
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