PPC440GRX-SPAFFFTS datasheet(63/88 Pages) AMCC

63 / 88 page

440GRx – PPC440GRx Embedded Processor

Revision 1.08 – October 15, 2007

AMCC Proprietary

Preliminary Data Sheet

Trace Interface

TrcBS0:2

Trace branch execution status.

I/O

3.3V tolerant

2.5V CMOS

TrcClk

Trace data capture clock, runs at 1/4 the frequency of the

processor.

3.3V tolerant

2.5V CMOS

TrcES0:4

Trace Execution Status is presented every fourth processor

clock cycle.

I/O

3.3V tolerant

2.5V CMOS

TrcTS0:6

Additional information on trace execution and branch status.

I/O

3.3V tolerant

2.5V CMOS

Power

VDD

+1.5V—Logic voltage.

n/a

OVDD

+3.3V—I/O (except DDR2 SDRAM and Ethernet).

n/a

EOVDD

+2.5V—I/O Ethernet.

n/a

SOVDD

+1.8V (DDR2) or +2.5V (DDR1)—I/O DDR SDRAM.

n/a

GND

Ground for logic and I/O voltage.

n/a

AVDD

+1.5V—Filtered voltage for system PLLs (analog).

n/a

AGND

Ground for system PLL voltage (analog).

n/a

EAVDD

+1.5V—Filtered voltage for Ethernet PLLs (analog).

n/a

EAGND

Ground for Ethernet PLL voltage (analog).

n/a

Reserved

To avoid noise pickup, the balls on this chip classified as

Reserved must be connected as shown in Table 8 on

page 55.

na/

n/a

Table 9. Signal Functional Description (Sheet 8 of 8)

Notes:

1. Receiver input has hysteresis

2. Must pull up (recommended value is 3k

Ω to OV

DD (EOVDD for Ethernet)

3. Must pull down (recommended value is 1k

Ω)

4. If not used, must pull up (recommended value is 3k

Ω to OV

DD (EOVDD for Ethernet)

5. If not used, must pull down (recommended value is 1k

Ω)

6. Strapping input during reset; pull-up or pull-down required

Signal Name

Description

I/O

Type

Notes

PPC440GRX-SPAFFFTS Datasheet(PDF) 63 Page - Applied Micro Circuits Corporation

PPC440GRX-SPAFFFTS Datasheet(HTML) 63 Page - Applied Micro Circuits Corporation

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