YMF795 datasheet(21/45 Pages) YAMAHA

21 / 45 page

YMF795

-21-

■Power-down control division diagram

Power-down of the LSI can be controlled for each divided internal function.

The power-down is controlled by Index 38h.

■Explanation of each bit

DP0

This is the bit to power off the whole digital section.

Consumption current of the digital part can be minimized because internal clock stops.

Contents of the registers are held but data in the FIFO are cleared.

AP1

This is the bit to power off the VREF circuit.

If AP1 is set to “1”, the whole analog section stops. Because an analog center voltage is made by VREF circuit.

AP2

This is the bit to power off the FM volume section, EQ circuit, speaker volume, and non-inverted amplifier side of

speaker output section.

SYNC

SDIN

SCLK

/RST

/IRQ

EQ1

VREF

Serial

I/F

VOL

32-step

RAM

Synthesizer

Simultaneous

Sound

Generation

4-tone

DAC

AMP

Timing Generator

VOL

32-step

FIFO

16b × 32w

EQ2

EQ3

SPOUT1

VREF

Controlled by

using DP bit

Controlled by

using AP4 bit

Controlled by

using AP3 bit

Controlled by

using AP1 bit

Controlled by

using AP2 bit

VOL

32-step

SPVSS

SPOUT2

YMF795 Datasheet(PDF) 21 Page - YAMAHA CORPORATION

YMF795 Datasheet(HTML) 21 Page - YAMAHA CORPORATION

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