M27C1024 datasheet(8/15 Pages) STMICROELECTRONICS

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tAVPL

VALID

AI00706

A0-A15

Q0-Q15

VPP

VCC

DATA IN

DATA OUT

tQVPL

tVPHPL

tVCHPL

tPHQX

tPLPH

tGLQV

tQXGL

tELPL

tGHQZ

tGHAX

PROGRAM

VERIFY

Figure 6. Programming and Verify Modes AC Waveforms

The associated transient voltage peaks can be

suppressed by complying with the two line output

control and by properly selected decoupling ca-

pacitors. It is recommended that a 0.1

µF ceramic

capacitor be used on every device between VCC

and VSS. This should be a high frequency capacitor

of low inherent inductance and should be placed

as close to the device as possible. In addition, a

4.7

µF bulk electrolytic capacitor should be used

between Vcc and VSS for every eight devices. The

bulk capacitor should be located near the power

supply connection point. The purpose of the bulk

capacitor is to overcome the voltage drop caused

by the inductive effects of PCB traces.

Programming

When delivered (and after each ’1’s erasure for UV

EPROM), all bits of the M27C1024 are in the ’1’

state. Data is introduced by selectively program-

ming ’0’s into the desired bit locations. Although

only ’0’s will be programmed, both ’1’s and ’0’s can

be present in the data word. The only way to

change a ’0’ to a ’1’ is by die exposure to ultraviolet

light (UV EPROM). The M27C1024 is in the pro-

gramming mode when VPP input is at 12.75V, E is

at VIL and P is pulsed to VIL. The data to be

programmed is applied to 16 bits in parallel to the

data output pins. The levels required for the ad-

dress and data inputs are TTL. VCC is specified to

be 6.25V

± 0.25V.

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows pro-

gramming of the whole array with a guaranteed

margin, in a typical time of 6.5 seconds. Program-

ming with PRESTO II consists of applying a se-

quenceof 100

µs programpulses toeach worduntil

a correct verify occurs (see Figure 7). During pro-

gramming and verify operation, a MARGIN MODE

circuit is automaticallyactivated in order to guaran-

tee that each cell is programmed with enough

margin. No overprogram pulse is applied since the

verify in MARGIN MODE provides necessary mar-

gin to each programmed cell.

DEVICE OPERATION (cont’d)

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