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AK4385VT Datasheet(PDF) 2 Page - Asahi Kasei Microsystems |
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AK4385VT Datasheet(HTML) 2 Page - Asahi Kasei Microsystems |
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2 / 23 page ![]() ASAHI KASEI [AK4385] MS0246-E-01 2006/01 - 2 - Ordering Guide AK4385ET -20 ∼ +85°C 16pin TSSOP (0.65mm pitch) AK4385VT -40 ∼ +85°C 16pin TSSOP (0.65mm pitch) AKD4385 Evaluation Board for AK4385 Pin Layout 1 MCLK LRCK BICK CSN CCLK CDTI Top View 2 3 4 5 6 7 8 DZFL DZFR VSS VDD AOUTL+ AOUTL- AOUTR+ AOUTR- 16 15 14 13 12 11 10 9 PDN SDTI PIN/FUNCTION No. Pin Name I/O Function 1 MCLK I Master Clock Input Pin An external TTL clock should be input on this pin. 2 BICK I Audio Serial Data Clock Pin 3 SDTI I Audio Serial Data Input Pin 4 LRCK I L/R Clock Pin 5 PDN I Power-Down Mode Pin When at “L”, the AK4385 is in the power-down mode and is held in reset. The AK4385 must be reset once upon power-up. 6 CSN I Chip Select Pin 7 CCLK I Control Data Input Pin 8 CDTI I Control Data Input Pin in serial mode 9 AOUTR- O Rch Negative Analog Output Pin 10 AOUTR+ O Rch Positive Analog Output Pin 11 AOUTL- O Lch Negative Analog Output Pin 12 AOUTL+ O Lch Positive Analog Output Pin 13 VSS - Ground Pin 14 VDD - Power Supply Pin 15 DZFR O Rch Data Zero Input Detect Pin 16 DZFL O Lch Data Zero Input Detect Pin Note: All input pins should not be left floating. |
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