MPC8280 datasheet(269/1386 Pages) FREESCALE

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60x Signals

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

7-11

Negated/High Impedance—Indicates that the MPC8280 does not need to retry the

last address tenure.

Timing Comments

Assertion—May occur as early as the second cycle following the assertion of TS

and must occur by the bus clock cycle immediately following the assertion of

AACK if an address retry is required.

Negation—Must occur during the second cycle after the assertion of AACK.

7.2.6

Data Bus Arbitration Signals

The data bus arbitration signals have no meaning in internal-only mode.

Like the address bus arbitration signals, data bus arbitration signals maintain an orderly process for

determining data bus mastership. Note that there is no data bus arbitration signal equivalent to the address

bus arbitration signal BR (bus request), because, except for address-only transactions, TS implies data bus

requests. For a detailed description on how these signals interact, see Section 8.5.1, “Data Bus

Arbitration.”

7.2.6.1

Data Bus Grant (DBG)

The data bus grant signal (DBG) is an output/input on the MPC8280.

7.2.6.1.1

Data Bus Grant (DBG)—Input

DBG an input when MPC8280 is configured to an external arbiter. The following are the state meaning

and timing comments for DBG.

State Meaning

Asserted—Indicates that the MPC8280 may, with the proper qualification, assume

mastership of the data bus. The MPC8280 derives a qualified data bus grant when

DBG is asserted and DBB and ARTRY are negated; that is, the data bus is not busy

(DBB is negated), and there is no outstanding attempt to perform an ARTRY of

the associated address tenure.

Negated—Indicates that the MPC8280 must hold off its data tenures.

Timing Comments

Assertion—May occur any time to indicate the MPC8280 is free to take data bus

mastership. It is not sampled until TS is asserted.

Negation—May occur at any time to indicate the MPC8280 cannot assume data

bus mastership.

7.2.6.1.2

Data Bus Grant (DBG)—Output

DBG signal is output when the MPC8280 configured to use the internal arbiter. Following are the state

meaning and timing comments for the DBG signal.

State Meaning

Asserted—Indicates that the external device may, with the proper qualification,

assume mastership of the data bus. A qualified data bus grant is defined as the

assertion of DBG, negation of DBB, and negation of ARTRY. The requirement for

the ARTRY signal is only for the address bus tenure associated with the data bus

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