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MPC8280 Datasheet(PDF) 278 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 278 Page - Freescale Semiconductor, Inc

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The 60x Bus
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
8-2
Freescale Semiconductor
8.2
Bus Configuration
The 60x bus supports separate bus configurations for internal masters and external bus masters.
•
Single-MPC8280 bus mode connects external devices by using only the memory controller. This
is described in Section 8.2.1, “Single-MPC8280 Bus Mode.”
•
The 60x-compatible bus mode, described in Section 8.2.2, “60x-Compatible Bus Mode,” enables
connections to other masters and 60x-bus slaves, such as an external L2 cache controller.
The figures in the following sections show how the MPC8280 can be connected in these two
configurations.
8.2.1
Single-MPC8280 Bus Mode
In single-MPC8280 bus mode, the MPC8280 is the only bus device in the system. The internal memory
controller controls all devices on the external pins. Figure 8-1 shows the signal connections for
single-MPC8280 bus mode.
Parking
Granting potential bus mastership without requiring a bus request from that device. This eliminates
the arbitration delay associated with the bus request.
Pipelining
Initiating a bus transaction before the current one finishes. This involves running an address tenure
for a new bus transaction before the data tenure for a current bus transaction completes.
Slave
The device addressed by the master. The slave is identified in the address tenure and is responsible
for sourcing or sinking the requested data for the master during the data tenure.
Snooping
Monitoring addresses driven by a bus master to detect the need for coherency actions.
Split-transaction A transaction with separate request and response tenures.
Tenure
The period of bus mastership. For MPC8280, there can be separate address bus tenures and data
bus tenures.
Transaction
A complete exchange between two bus devices. A typical transaction is composed of an address
tenure and a data tenure, which may overlap or occur separately from the address tenure. A
transaction can minimally consist of an address tenure alone.
Table 8-1. Terminology (continued)
Term
Definition



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