Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

MPC8280 Datasheet(PDF) 280 Page - Freescale Semiconductor, Inc

Part # MPC8280
Description  PowerQUICC??II Family Reference Manual
PDF  1386 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 280 Page - Freescale Semiconductor, Inc

Back Button MPC8280 Datasheet HTML 276Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 277Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 278Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 279Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 280Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 281Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 282Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 283Page - Freescale Semiconductor, Inc MPC8280 Datasheet HTML 284Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 280 / 1386 page
background image
The 60x Bus
MPC8280 PowerQUICC II Family Reference Manual, Rev. 1
8-4
Freescale Semiconductor
Figure 8-2. 60x-Compatible Bus Mode
8.3
60x Bus Protocol Overview
Typically, 60x bus accesses consist of address and data tenures, which in turn each consist of three
phases—arbitration, transfer, and termination, as shown in Figure 8-3.. The independence of the tenures is
indicated by showing the data tenure overlap the next address tenure, which allows split-bus transactions
to be implemented at the system level in multiprocessor systems. Figure 8-3 shows a data transfer that
consists of a single-beat transfer of as many as 256 bits. Four-beat burst transfers of 32-byte cache blocks
require data transfer termination signals for each beat of data. Note that the MPC8280 supports port sizes
of 8, 16, 32, and 64 bits and requires the additional bus signal, PSDVAL, which is not defined by the 60x
BR
BG
TS
A[0–31]
TT[0–4]
TSIZ[0–3]
TBST
CI
WT
GBL
AACK
ARTRY
DBG
D[0–63]
DP[0–7]
TA
TEA
MPC8280
I/O
MEM
External Device
BR
BG
DBG
Latch
Latch &
DRAM MUX
Memory Control Signals
AP[0–3]
TS
APE



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com