MPC8280 datasheet(307/1386 Pages) FREESCALE

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The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-31

8.7.1

Support for the lwarx/stwcx. Instruction Pair

The load word and reserve indexed (lwarx) and the store word conditional indexed (stwcx.) instructions

provide a way to update memory atomically by setting a reservation on the load and checking that the

reservation is still valid before the store is performed. In the MPC8280, reservations are made on behalf

of aligned, 32-byte sections of the memory address space.

The reservation (RSRV) output signal is driven synchronously with the bus clock and reflects the status of

the reservation coherency bit in the reservation address register.

Note that each external master must do its own snooping; the MPC8280 does not provide external

reservation snooping.

8.7.2

TLBISYNC Input

The TLBISYNC input permits hardware synchronization of changes to MMU tables when the MPC8280

and another DMA master share the MMU translation tables in system memory. A DMA master asserts

TLBISYNC when it uses shared addresses that the MPC8280 could change in the MMU tables during the

DMA master’s tenure.

When the TLBISYNC input is asserted, the MPC8280 cannot complete any instructions past a tlbsync

instruction. Generally, during the execution of an eciwx or ecowx instruction, the selected DMA device

should assert the MPC8280’s TLBISYNC signal and hold it asserted during its DMA tenure if it is using

a shared translation address. Subsequent instructions by the MPC8280 processor should include a sync and

tlbsync instruction before any MMU table changes are performed. This prevents the MPC8280 from

making disruptive table changes during the DMA tenure.

8.8

Little-Endian Mode

The MPC8280 supports a little-endian mode in which low-order address bits are operated on (munged)

based on the size of the requested data transfer. This mode allows a little-endian program running on the

processor with a big-endian memory system to offset into a data structure and receive the same results as

it would if it were operating on a true little-endian processor and memory system. For example, writing a

word to memory as a word operation on the bus and then reading in the second byte of that word as a byte

operation on the bus.

NOTE

When the processor is selected for little-endian operation, the bus interface

is still operating in big-endian mode. That is, byte address 0 of a double

word (as selected by A[29–31] on the bus—after the internal address

munge) still selects the most significant (left most) byte of the double word

on D[0–7]. If the processor interfaces with a true little-endian environment,

the system may need to perform byte-lane swapping or other operations

external to the processor.

MPC8280 Datasheet(PDF) 307 Page - Freescale Semiconductor, Inc

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