MPC8280 datasheet(304/1386 Pages) FREESCALE

304 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-28

Freescale Semiconductor

Figure 8-10 shows a burst transfer to a 32-bit port. Each double-word burst beat is divided into two

port-sized beats such that the four double words are transferred in eight beats.

Figure 8-10. Burst Transfer to 32-Bit Port Size

8.5.6

Data Bus Termination by Assertion of TEA

If a device initiates a transaction that is not supported by the MPC8280, the MPC8280 signals an error by

asserting TEA. Because the assertion of TEA is sampled by the device only during the data tenure of the

bus transaction, the MPC8280 ensures that the device master receives a qualified data bus grant by

asserting DBG before asserting TEA. The data tenure is terminated by a single assertion of TEA regardless

of the port size or whether the data tenure is a single-beat or burst transaction. This sequence is shown in

Figure 8-11.. In Figure 8-11. the data bus is busy at the beginning of the transaction, thus delaying the

assertion of DBG. Note that data errors (parity and ECC) are reported not by assertion of TEA but by

assertion of MCP.

Because the assertion of TEA is sampled by the device only during the data tenure of the bus transaction,

the MPC8280 ensures that the device receives a qualified data bus grant by asserting DBG before asserting

TEA. The data tenure is terminated by a single assertion of TEA regardless of the port size or whether the

data tenure is a single-beat or burst transaction.

CLKOUT

ADDR + ATTR

AACK

DBG

PSDVAL

D[0–31]

MPC8280 Datasheet(PDF) 304 Page - Freescale Semiconductor, Inc