MPC8280 datasheet(301/1386 Pages) FREESCALE

301 / 1386 page

The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

8-25

•

External masters connected to the 60x bus must assert DBB only for the duration of its data tenure.

External masters should not use DBB to prevent other masters from using the data bus after their

data tenure has ended.

8.5.2

Data Streaming Mode

The MPC8280 supports a special data streaming mode that can improve bus performance in some

conditions. Generally, the bus protocol requires one idle cycle between any two data tenures. This idle

cycle is essential to prevent contention on the data bus when the driver of the data is changing. However,

when the driver on the data bus is the same for both data tenures, this idle cycle may be omitted.

In data streaming mode, the MPC8280 omits the idle cycle where possible. MPC8280 applications often

require data stream transfers of more than 4 x 64 bits. For example, the ATM cell’s payload is 6 x 64 bits.

All this data is driven from a single device on the bus, so data-streaming saves a cycle for such a transfer.

When data-streaming mode is enabled, transactions initiated by the core are not affected, while

transactions initiated by other bus masters within the chip omit the idle cycle if the data driver is the same.

Note that data streaming mode cannot be enabled when the MPC8280 is in 60x-compatible bus mode and

a device that uses DBB is connected to the bus. This restriction is due to the fact that a MPC8280 for which

data streaming mode is enabled may leave DBB asserted after the last TA of a transaction and this is a

violation of the strict bus protocol. The data streaming mode is enabled by setting BCR[ETM].

8.5.3

Data Bus Transfers and Normal Termination

The data transfer signals include D[0–63] and DP[0–7]. For memory accesses, the data signals form a

64-bit data path, D[0–63], for read and write operations.

The MPC8280 handles data transfers in either single-beat or burst operations. Single-beat operations can

transfer from 1 to 24 bytes of data at a time. Burst operations always transfer eight words in four

double-word beats. A burst transaction is indicated by the assertion of TBST by the bus master. A

transaction is terminated normally by asserting TA.

The three following signals are used to terminate the individual data beats of the data tenure and the data

tenure itself:

•TA indicates normal termination of data transactions. It must always be asserted on the bus cycle

coincident with the data that it is qualifying. It may be withheld by the slave for any number of

clocks until valid data is ready to be supplied or accepted.

•

Asserting TEA indicates a nonrecoverable bus error event. Upon receiving a final (or only)

termination condition, the MPC8280 always negates DBB for one cycle, except when fast data bus

grant is performed.

•

Asserting ARTRY causes the data tenure to be terminated immediately if the ARTRY is for the

address tenure associated with the data tenure in operation (the data tenure may not be terminated

due to address pipelining). The earliest allowable assertion of TA depends directly on the latest

possible assertion of ARTRY.

Figure 8-8 shows both a single-beat and burst data transfer. The MPC8280 asserts TA to mark the cycle in

which data is accepted. In a normal burst transfer, the fourth assertion of TA signals the end of a transfer.

MPC8280 Datasheet(PDF) 301 Page - Freescale Semiconductor, Inc

MPC8280 Datasheet(HTML) 301 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL