MPC8280 datasheet(300/1386 Pages) FREESCALE

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The 60x Bus

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

8-24

Freescale Semiconductor

one-level pipelining). When the internal arbiter counts a pipeline depth of two (two assertions of

AACK before the assertion of the current data tenure) it negates all address bus grant (BG) signals.

•

No-pipeline mode—The MPC8280 does not assert AACK until the corresponding data tenure

ends.

8.5

Data Tenure Operations

This section describes the operation of the MPC8280 during the data bus arbitration, transfer, and

termination phases of the data tenure.

NOTE: External Master Writes to DPRAM

DPRAM is clocked by the CPM clock and not by the 60x bus clock.

Therefore, data is not latched at the TA assertion cycle during writes to

DPRAM from the external master. Instead, the data is latched earlier. It is

necessary, then, that the external master drive the data bus immediately after

DBG and hold the data bus until after TA.

8.5.1

Data Bus Arbitration

The beginning of an address transfer, marked by the assertion of transfer start (TS), is also an implicit data

bus request provided that the transfer type signals (TT[0–4]) indicate that the transaction is not

address-only.

The MPC8280 arbiter supports one external master and uses DBG to grant the external master data

bus.The DBG signals are not asserted if the data bus, which is shared with memory, is busy with a

transaction.

A qualified data bus grant (QDBG) can be expressed as the assertion of DBG while DBB and ARTRY

(associated with the data bus operation) are negated.

Note that the MPC8280 arbiter should assert DBG only when it is certain that the first TA will be asserted

with or after the associated ARTRY. The MPC8280 DBG is asserted with TS if the data bus is free and if

the PPC_ACR[DBGD] = 0. If PPC_ACR[DBGD] = 1, DBG is asserted one cycle after TS if the data bus

is not busy. The DBG delay should be used to ensure that ARTRY is not asserted after the first or only TA

assertion. For the programming model, see Section 4.3.2.2, “60x Bus Arbiter Configuration Register

(PPC_ACR).”

Note that DBB should not be asserted after the data tenure is finished. Assertion of DBB after the last TA

causes improper operation of the bus. (MPC8280 internal masters do not assert DBB after the last TA.)

Note the following:

•

External bus arbiters must comply with the following restriction on assertion of DBG which is

connected to the MPC8280. In case the data bus is not busy with the data of a previous transaction

on the bus, external arbiter must assert DBG in the same cycle in which TS is asserted (by a master

which was granted the bus) or in the following cycle. In case the external arbiter asserts DBG on

the cycle in which TS was asserted, PPC_ACR[DBGD] should be zero. Otherwise,

PPC_ACR[DBGD] should be set.

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