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HE84G762B Datasheet(PDF) 5 Page - King blillion Electronics Co.,Ltd. |
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HE84G762B Datasheet(HTML) 5 Page - King blillion Electronics Co.,Ltd. |
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5 / 60 page ![]() KING BILLION ELECTRONICS CO., LTD 駿 億 電 子 股 份 有 限 公 司 HE84G762B HE80004 Series June 1, 2004 5 V0.92 This specification is subject to change without notice. Please contact sales person for the latest version before use. Pin Name Pin # I/O Description LCAP2B 53 O Charge Pump Capacitor Pin. LCAP2A 54 O Charge Pump Capacitor Pin. LCAP1A 55 O Charge Pump Capacitor Pin. LCAP1B 56 O Charge Pump Capacitor Pin. LCAP3A 57 O Charge Pump Capacitor Pin. LVREG 58 O Voltage Regulator Output. VDD is regulated to generate LVREG, which is in turns pumped to LVP. Adjust resistor between LGS1 and LVREG to set LVREG voltage. LGS1 59 I Regulator Voltage Setting LVAG 60 O Reference Voltage Output. Fixed 0.9 Volt DC reference voltage VDD_LCD(VDDA) 61 P Power supply for LCD charge-pump. GND_LCD(VSSA) 62 P LCD power system ground. OAC 63 O LCD frame signal for interfacing with LCD segment extender KD80. OCCK 64 O LCD data load pin for interfacing with LCD segment extender KD80. GND 65 P Power ground Input. OPO 66 O Output of OP Amp. OPIP 67 I Non-inverting input of OP Amp. OPIN 68 I Inverting input of OP Amp. DAO 69 O Alternate output of DAC. VO 70 O DAC Output. RSTP_N 71 I System Reset input pin. Level trigger, active low on this pin will put the chip in reset state. FXO, FXI 72, 73 O, B External fast clock pin. Two types of oscillator can be selected by MO_FXTAL (‘0’ for RC type and ‘1’ for crystal type). For RC type oscillator, one resistor needs to be connected between FXI and GND. For crystal oscillator, one crystal needs to be placed between FXI and FXO. Please refer to application circuit for details. TSTP_P 74 I Test input pin. Please bond this pad and reserve a test point on PCB for debugging. But for improving ESD, please connect this point with zero Ohm resistor to GND. SXO, SXI 75, 76 O, I External slow clock pins. Slow clock is clock source for LCD display, TIMER1, Time-Base and other internal blocks. Both crystal and RC oscillator are provided. The slow clock type can be selected by mask option MO_SXTAL. Choose ‘0’ for RC type and ‘1’ for crystal oscillator. VX 77 I Input pin for x32 PLL circuit. Connect to external resistor and capacitors as shown in application circuit. VDD 78 P Positive power Input. A 0.1 µF decoupling capacitors should be placed as close to IC VDD and GND pads as possible for best decoupling effect. PRT10[7..0] 79~86 B 8-bit bi-directional I/O port 10. The output type of I/O pad can also be selected by mask option MO_10PP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O pad as input pad, “1” must be outputted before reading. PRTD[7..2] PRTD[1]/SIN PRTD[0]/SOUT 87~94 B 8-bit bi-directional I/O port D. The output type of I/O pad can also be selected by mask option MO_DPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, ‘1’ must be outputted before reading the pin. PRTD[7..2] can be used as wake-up pins. PRTD[7..6] can be as external interrupt sources. PRTD[1] shares pad with UART Receiver SIN pin. PRTD[0] shares pad with UART transmitter SOUT pin. PRTC[7:0] 95~102 B 8-bit bi-directional I/O port C. The output type of I/O pad can also be selected by mask option MO_CPP[7..0] (‘1’ for push-pull and ‘0’ for open-drain). As the output structure of I/O pad does not contain tri-state buffer. When using the I/O as input, ‘1’ must be outputted before reading the pin. VDD_RAM 103 P Dedicated power input for RAM IRO 104 O The Infrared output. PWM 105 O The PWM output can drive speaker or buzzer directly. Using VDD & PWM to drive output device. GND_PWM 106 P Dedicated Ground for PWM output. CMSG[32..79] 107~154 O COM[32..79] pads are shared with SEG[95..48] outputs. The functions of the pads to be COM drivers or SEG drivers can be selected by mask option MO_COM[1..0]. Please |
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