RT9641BGS datasheet(6/11 Pages) RICHTEK

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RT9641A/B

DS9641A/B-11 March 2007

www.richtek.com

voltage goes up to 0.8V (typically 5ms after POR). In case

of an under-voltage on any of the outputs or an over

temperature event, this pin is used to report the fault

condition by being pulled to 5VSB.

DLA (Pin 10)

Connect this pin to the gates of suitable N-MOSFETs,

which in active states, are used to switch in the ATX 3.3V

and 5V outputs into the 3.3VDUAL and 5VDUAL outputs,

respectively.

5VDLSB (Pin 11)

Connect this pin to the gate of a suitable P-MOSFET or

bipolar PNP. In sleep states, this transistor is switched

on, connecting the ATX 5VSB output to the 5VDUALregulator

output. When PNP is used, it is recommanded to use a

100

Ω base resistor for base current limiting.

5VDL (Pin 12)

Connect this pin to the DLA through an 180k

Ω resistor for

distinguishing S0 state from S3/S5.

SS (Pin 13)

Connect a small ceramic capacitor (0.1

μF recommended)

from this pin to GND. The internal Soft-start (SS) current

source along with the external capacitor creates a voltage

ramp used to control the ramp-up of the output voltages.

Pulling this pin low with an open-drain device shuts down

all the output as well as forces the FAULT pin low. The CSS

capacitor is also used to provide a controlled S4/S5 to

active transition delay time.

12V (Pin 14)

Connect this pin to the ATX (or equivalent) 12V output.

This pin is used to monitor the status of the power supply

as well as provide bias for the NMOS-compatible output

drivers. 12V presence at the chip in the absence of bias

voltage, or severe 12V brownout during active states (S0,

S1) operation can lead to chip misbehavior. RT9641A/B

refuses entering active state before 12V power ready.

DRV2 (Pin 15)

For the 2.5V RDRAM systems, connect this pin to the

base of a suitable NPN transistor. This pass transistor

regulates the 2.5V(2.6V) output from the ATX 3.3V during

active states operation. For 3.3V SDRAM systems connect

Functional Pin Description

5VSB (Pin 1)

Provide a 5V bias supply for the IC to this pin by connecting

it to the ATX 5VSB output. This pin also provides the base

bias current for all the external NPN transistors controlled

by the IC. The voltage at this pin monitored for power-on

reset (POR) purposes.

EN3VDLand EN5VDL (Pin 2 and Pin5)

These pins control the logic governing the output behavior

in response to S3 and S4/S5 requests. These are digital

inputs whose status can only be changed during active

states operation or during chip shutdown (SS pin grounded

by external open-drain device). The input information is

latched-in when entering a sleep state, as well as following

5VSB POR release or exit from shutdown.

3V3DLSB (Pin 3)

Connect this pin to the base of a suitable NPN transistor.

In sleep states, this transistor is used to regulate the

voltage at 3V3DL pin to 3.3V.

3V3DL (Pin 4)

Connect this pin to the 3.3V dual output (VOUT1). In sleep

states, the voltage at this pin is regulated to 3.3V; in active

states, ATX 3.3V output is delivered to this node through a

fully on N-MOS transistor. During all operating states, this

pin is monitored for under-voltage events.

S3 and S5 (Pin 6 and Pin7)

These pins switch the IC's operating state from active (S0,

S1) to S3 and S4/S5 sleep states. Connect S3 to SLP_S3

and S5 to SLP_S5. These are digital inputs featuring

internal 50k

Ω(typical) resistor pull-up to 5VSB. Internal

circuitry de-glitches the S3 pin for disturbances.

GND (Pin 8)

Signal ground for the IC. All voltage levels are measured

with respect to this pin.

FAULT/MSEL (Pin 9)

This is a multiplexed function pin allowing the setting of

the memory output voltage to either 2.5V(2.6V) or

3.3V(3.43V) (for RDRAM or SDRAM memory systems).

The memory voltage setting is latched-in when SS pin

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