PC312XDP512F0CFVR datasheet(874/1350 Pages) FREESCALE

Part #	PC312XDP512F0CFVR

Description	Covers, S12XD, S12XB & S12XA Families

PDF	1350 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

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Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.17

874

Freescale Semiconductor

22.3.2.63 Port AD0 Data Direction Register 1 (DDR1AD0)

Read: Anytime.

Write: Anytime.

This register configures pins PAD[07:00] as either input or output.

76543210

DDR1AD07

DDR1AD06

DDR1AD05

DDR1AD04

DDR1AD03

DDR1AD02

DDR1AD01

DDR1AD00

Reset

00000000

Figure 22-65. Port AD0 Data Direction Register 1 (DDR1AD0)

Table 22-58. DDR1AD0 Field Descriptions

Field

Description

7–0

DDR1AD0[7:0]

Data Direction Port AD0 Register 1

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is

read on PTAD01 register, when changing the DDR1AD0 register.

Note: To use the digital input function on port AD0 the ATD0 digital input enable register (ATD0DIEN) has to

be set to logic level “1”.

PC312XDP512F0CFVR Datasheet(PDF) 874 Page - Freescale Semiconductor, Inc