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PI7C9X130 Datasheet(PDF) 13 Page - Pericom Semiconductor Corporation |
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PI7C9X130 Datasheet(HTML) 13 Page - Pericom Semiconductor Corporation |
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13 / 157 page ![]() PI7C9X130 PCI EXPRESS TO PCI-X BRIDGE Page 13 of 157 PERICOM SEMICONDUCTOR September 2007 - Rev 1.2 1 INTRODUCTION PI7C9X130 is a PCIe-to-PCI/PCI-X bridge. PI7C9X130 is compliant with the PCI Express Base Specification, Revision 1.1, the PCI Express Card Electromechnical Specification, Revision 1.1, the PCI Local Bus Specification, Revision 3.0 and PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X130 supports transparent and non-transparent mode of operations. Also, PI7C9X130 supports forward and reverse bridging. In forward bridge mode, PI7C9X130 has an x4 PCI Express upstream port and a 64-bit PCI/PCI-X downstream port. The 64-bit PCI-X downstream port is 133MHz capable (see Figure 1-1). In reverse bridge mode, PI7C9X130 has a 64-bit PCI-X upstream port and an x4 PCI Express downstream port. PI7C9X130 configuration registers are backward compatible with existing PCI bridge software and firmware. No modification of PCI bridge software and firmware is needed for the original operation. Figure 1-1 PI7C9X130 Topology X4 PCI Express Link PCI-X 64-bit, 133MHz Bus Rx Tx 1.1 PCI EXPRESS FEATURES • Compliant with PCI Express Base Specification, Revision 1.1 • Compliant with PCI Express Card Electromechnical Specification, Revision 1.1 • Compliant with PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0 • Physical Layer interface (x4 link with 2.5Gb/s data rate) • Lane polarity toggle • Virtual isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) • ASPM support • Beacon support • CRC (16-bit), LCRC (32-bit) • ECRC and advanced error reporting • PRBS (Pseudo Random Bit Sequencing) generator/checker for chip testing • Maximum payload size to 512 bytes |
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