PCAL9722HNMP datasheet(30/63 Pages) NXP

30 / 63 page

NXP Semiconductors

PCAL9722

Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and

reset

8 Application design-in information

PCAL9722

P0_0

P0_1

SCLK

SDOUT

SDIN

VDD

SCLK

MISO

MOSI

P0_2

P0_3

MASTER

CONTROLLER

VSS

VDD(SPI) = 1.8 V

controlled

switch

enable

INT

VDD(P)

INT

10 k

SUBSYSTEM 1

(e.g., alarm system)

ALARM(1)

P0_4

P0_5

P0_6

P0_7

RESET

VDD(P)

aaa-015943

P1_0

P1_1

P1_2

P1_3

P1_4

P1_5

P1_6

P1_7

VDD(SPI)

ADDR

KEYPAD

10 k

10 k (× 7)

P2_5

P2_4

P2_3

P2_2

P2_1

P2_0

STATUS

MONITOR

VSS

Device address configured as 0100 000x for this example.

P0_0 and P0_2 through P1_0 are configured as inputs.

P0_1 and P1_1 through P1_7, and P2_0 through P2_5 are configured as outputs.

1. External resistors are required for inputs (on P port) that may float. If a driver to an input will never let the input float,

a resistor is not needed with internal pull-up or pull-down resistor option. If an output in the P port is configured as an

output, there is no need for external pull-up resistors.

Figure 14. Typical application

8.1 Output drive strength control

The Output drive strength registers allow the user to control the output drive level of the GPIO. Each GPIO can

be configured independently to one of the four possible output current levels. By programming these bits the

user is changing the number of transistor pairs or ‘fingers’ that drive the I/O pad.

Figure 15 shows a simplified output stage. The behavior of the pad is affected by the Configuration register, the

output port data, and the current control register. When the Current Control register bits are programmed to 01b,

then only two of the fingers are active, reducing the current drive capability by 50 %.

PCAL9722

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.1 — 1 May 2023

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