74LVC3GU04DP datasheet(7/16 Pages) NXP

7 / 16 page

74LVC3GU04_5

Product data sheet

Rev. 05 — 5 October 2007

7 of 16

NXP Semiconductors

74LVC3GU04

Triple inverter

12. Waveforms

Measurement points are given in Table 9.

VOL and VOH are typical output voltage levels that

occur with the output load.

Test data is given in Table 10.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe

capacitance.

RT = Termination resistance should be equal to the

output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching

times.

Fig 7.

The input (nA) to output (nY) propagation

delays

Fig 8.

Load circuitry for switching times

mna344

tPHL

tPLH

nA input

nY output

GND

VOH

VOL

VEXT

VCC

mna616

DUT

Table 9.

Measurement points

Supply voltage

Input

Output

VCC

1.65 V to 1.95 V

0.5

× V

0.5

× V

2.3 V to 2.7 V

0.5

× V

0.5

× V

2.7 V

1.5 V

3.0 V to 3.6 V

1.5 V

4.5 V to 5.5 V

0.5

× VCC

0.5

× V

Table 10.

Test data

Supply voltage

Input

Load

VEXT

VCC

tr =tf

tPLH, tPHL

1.65 V to 1.95 V

VCC

≤ 2.0 ns

30 pF

1 k

Ω

open

2.3 V to 2.7 V

VCC

≤ 2.0 ns

30 pF

500

Ω

open

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

3.0 V to 3.6 V

2.7 V

≤ 2.5 ns

50 pF

500

Ω

open

4.5 V to 5.5 V

VCC

≤ 2.5 ns

50 pF

500

Ω

open

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