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STCF03 Datasheet(PDF) 15 Page - STMicroelectronics |
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STCF03 Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 35 page ![]() Introduction STCF03 15/35 7.5 Start and stop conditions Both DATA and CLOCK lines remain HIGH when the bus is not busy. As shown in Figure 5 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition 7.6 Byte format Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse. Any change in the SDA line at this time will be interpreted as a control signal. Figure 5. Timing diagram on I2C Bus Figure 6. Bit transfer |
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