TMP1941AF datasheet(49/354 Pages) TOSHIBA

49 / 354 page

TMP1941AF

2003-03-27

TMP1941AF-9

Core Processor

The TMP1941AF contains a high-performance 32-bit core processor called the TX19. For a detailed

description of the core processor, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.

Be sure to read Section 21, Notations, Precautions and Restrictions, before using this product.

Functions unique to the TMP1941AF, which are not covered in the architecture manual, are described below.

3.1

Reset Operation

To reset the TMP1941AF, RESET must be asserted for at least 12 system clock periods after the power

supply voltage and the internal high-frequency oscillator have stabilized. This time is typically 2.4

µs at 40

MHz when the on-chip PLL is utilized, and 4.8

µs otherwise. After a reset, either the PLL-multiplied clock

or an external clock is selected, depending on the logic state of the PLLOFF pin. By default, the selected

clock is geared down to 1/8 for internal operation.

The following occurs as a result of a reset:

•

The System Control Coprocessor (CP0) registers within the TX19 core processor are initialized.

For details, refer to the 32-Bit TX System RISC TX19 Core Architecture manual.

•

The Reset exception is taken. Program control is transferred to the exception handler at a

predefined address. This predefined location is called exception vector, which directly indicates the

start of the actual exception handler routine. The Reset exception is always vectored to virtual

address 0xBFC0_0000 (which is the same as for the Nonmaskable Interrupt exception).

•

All on-chip I/O peripheral registers are initialized.

•

All port pins, including those multiplexed with on-chip peripheral functions, are configured as

either general-purpose inputs or general-purpose outputs.

Note:

A reset operation does not affect the contents of the on-chip RAM.

TMP1941AF Datasheet(PDF) 49 Page - Toshiba Semiconductor