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TMPR4937 Datasheet(PDF) 91 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 91 Page - Toshiba Semiconductor |
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91 / 552 page  Chapter 5 Configuration Registers 5-11 5.2.5 Clock Control Register (CLKCTR) 0xE020 Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them, wait at least 128 CPU clock cycles after they are set. 63 48 Reserved : Type : Initial value 47 32 Reserved : Type : Initial value 31 26 25 24 23 22 21 20 19 18 17 16 DMA1CKD ACLCKD PIOCKD DMACKD PCICCKD 1 TM0CKD TM1CKD TM2CKD SIO0CKD SIO1CKD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 0 1 0 0 0 0 0 : Initial value 15 10 9 8 7 6 5 4 3 2 1 0 Reserved DMA1RST ACLRST PIORST DMA0RST PCICRST 1 TM0RST TM1RST TM2RST SIO0RST SIO1RST R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Type 0 0 0 0 0 1 0 0 0 0 0 : Initial value Bit Mnemonic Field Name Description Initial Value Read/Write 63:27 ⎯ Reserved ⎯ ⎯ ⎯ 26 DMA1CKD DMAC1 Clock Disable Controls clock pulses for the DMA controller 1. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 25 ACLCKD ACLC Clock Disable Controls clock pulses for the AC-link controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 24 PIOCKD PIO Clock Disable Controls clock pulses for the parallel IO controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 23 DMA0CKD DMAC0 Clock Disable Controls clock pulses for the DMA controller 0. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 22 PCICKD PCIC Clock Disable Controls clock pulses for the PCI controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 21 ⎯ ⎯ Always set this bit to 1. 1 R/W 20 TM0CKD Timer 0 Clock Disable Controls clock pulses for the TMR0 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 19 TM1CKD Timer 1 Clock Disable Controls clock pulses for the TMR1 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W 18 TM2CKD Timer 2 Clock Disable Controls clock pulses for the TMR2 controller. 0 = Supply clock pulses. 1 = Do not supply clock pulses. 0 R/W Figure 5.2.5 Clock Control Register (1/2) |
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