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TMPR4937 Datasheet(PDF) 117 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 117 Page - Toshiba Semiconductor |
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117 / 552 page ![]() Chapter 7 External Bus Controller 7-17 Figure 7.3.11 ACK* Input Timing (Burst Read Cycle) Figure 7.3.12 ACK* Input Timing (Burst Write Cycle) SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) Latch Data Acknowledge ACK* Acknowledge ACK* EBCCRn.SHWT=0 Latch Data 2 clocks 2 clocks SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) EBCCRn.SHWT=0 Acknowledge ACK* Acknowledge ACK* 3 clocks 3 clocks 4 clocks 4 clocks |
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