TMPR4937 datasheet(166/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-10

8.3.7.1

Channel Register Settings During Single Address Transfer

Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If

these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit

(CFERR) of the DMA Channel Status Register (DMCSRn) is set and DMA transfer is not

performed.

For Burst transfer, +8, 0, or –8 can be set to the DMA Source Address Increment Register

(DMSAIRn). Setting 0 is only possible during transfer from memory to external I/O. A

Configuration Error will result if the value “0” is set during transfer from external I/O to memory

or during Memory Fill transfer.

If the setting of the DMA Source Address Increment Register (DMSAIRn) is negative and the

transfer setting size is 2 bytes or larger, then set the DMA Source Address Register (DMSARn)

with 1 to 3 low-order bits complemented.

•

If the transfer size is 2 bytes, set the DMSARn with the low-order 1 bit complemented.

•

If the transfer size is 4 bytes, set the DMSARn with the low-order 2 bits complemented.

•

If the transfer size is 8 bytes or larger, set the DMSARn with the low-order 3 bits

complemented.

Example: When the transfer address is 0x0_0001_0000, the DMA Source Address

•

DMSAIRn setting is “0” or greater: 0x0_0001_0000

•

DMSAIRn setting is a negative value: 0x0_0001_0007

During Single Address transfer, the DMA Destination Address Register (DMDARn) and DMA

Destination Address Increment Register (DMDAIRn) settings are ignored.

Table 8.3.2 Channel Register Setting Restrictions During Single Address Transfer

DMSARn[2:0]

Transfer Setting

Size

(DMCCRn.XFSZ)

DMSAIRn is “0” or

greater

DMSAIRn setting is a

negative value

DMSAIRn[2:0]

DMCNTRn[2:0]

1 Byte

***

2 Bytes

**0

4 Bytes

*00

8 Bytes

000

111

000

4 Double Words

8 Double Words

16 Double Words

32 Double Words

000

111

8/0/-8

000

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