TMPR4937 datasheet(175/552 Pages) TOSHIBA

175 / 552 page

Chapter 8 DMA Controller

8-19

Figure 8.3.5 DMA Command Descriptor Chain

The sequence of Chain DMA transfer is as follows below.

Select DMA request signal

When performing external I/O or internal I/O DMA, set the DMA Request Select field

(PCFG.DMASEL) of the Pin Configuration Register.

Set the Master Enable bit

Set the Master Enable bit (DMMCR.MSTEN) of the DMA Master Control Register.

Structure of the DMA command Descriptor chain

Construct the DMA Command Descriptor Chain in memory.

Set the Count Register

Set “0” to the DMA Count Register (DMCNTRn) .

Sets the DMA Source Address Increment Register (DMSAIRn) and DMA destination Address

Increment Register (MMDAIRn).

Clear the DMA Channel Status Register (DMCSRn)

Clear the status of the previous DMA transfer.

Set the DMA Channel Control Register (DMCCRn).

“A”

+08

+10

+18

+20

+28

+30

+38

“B”

+08

+10

+18

+20

+28

+30

+38

“C”

+08

+10

+18

+20

+28

+30

+38

“D”

+08

+10

+18

+20

+28

+30

+38

“E”

+08

+10

+18

+20

+28

+30

+38

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