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TMPR4937 Datasheet(PDF) 239 Page - Toshiba Semiconductor |
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TMPR4937 Datasheet(HTML) 239 Page - Toshiba Semiconductor |
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239 / 552 page  Chapter 9 SDRAM Controller 9-23 9.4.4 ECC Control Register (ECCCR) 0xA000 63 56 55 48 MDLNO VERNO 0x10 0x10 :Type :Initial value 47 32 Reserved :Type :Initial value 31 24 23 17 16 DECC Reserved DM R/W R/W :Type 0 0 0 0 0 0 0 0 0 :Initial value 15 11 10 9 8 7 1 0 Reserved MEB MEI SEI Reserved ECCE R/W R/W R/W R/W :Type 0 0 0 0 :Initial value Bit Mnemonic Field Name Description Read/Write 63:56 MDLNO Model Number Model Number (Default: 0x10) Indicates the model number. The default value for the TX4937 is 0x10. This field is Read Only. R 55:48 VERNO Version Number Address Mask (Default: 0x10) Indicates the version number. The default value for the TX4937 is 0x10. This field is Read Only. R 47:32 — — Reserved ⎯ 31:24 DECC Diagnostic ECC Diagnostic ECC (Default: 0x00) The value set by this field is output from CB[7:0] as the check code when the DM bit is set to “Enable.” R/W 23:17 — — Reserved ⎯ 16 DM Diagnostic Mode ECC Diagnostic Mode (Default: 0) Specifies whether to use the Diagnostic Mode. 0: Disable 1: Enable R/W 15:11 — — Reserved ⎯ 10 MEB Multi-Bit Error Bus Error Enable Multi-Bit Error Bus Error Enable (Default: 0) Specifies whether to generate a bus error when a multi-bit error occurs. When this function is enabled, an NMI is generated for RMW* errors occurring during a Write operation to the TX49/H3 core. Bus errors are generated for all other operations. 0: Disable 1: Enable R/W 9 MEI Multi-Bit Error Interrupt Enable Multi-Bit Error Interrupt Enable (Default: 0) Specifies whether to generate an interrupt during a multi-bit error. 0: Disable 1: Enable R/W Figure 9.4.4 ECC Control Register (1/2) |
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