TMPR4937 datasheet(305/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-47

10.4.21 P2G Interrupt Mask Register (P2GMASK) 0xD098

Reserved

PMSCIE PMEESIE PMECLRIE M66ENIE

Reserved

R/W

: Type

0x0

: Initial value

Reserved

: Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:25

Reserved

⎯

PMSCIE

Power

Management

State Change

Interrupt Enable

Power Management State Change Interrupt Enable (Default: 0x0)

Generates an interrupt when the PowerState field of the Power

Management Register (PMCSR) is rewritten.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

PMEESIE

PME_En Set

Interrupt Enable

PME_En Set Interrupt Enable (Default: 0x0)

Generates an interrupt when the PME_En bit of the PMCSR Register is

set.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

PMECLRIE

PME Status Clear

Interrupt Enable

PME_Status Clear Interrupt Enable (Default: 0x0)

Generates an interrupt when the PME_Status bit of the PMCSR Register is

cleared.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

M66ENIE

66 MHz Drive

Interrupt Enable

M66EN Detected Interrupt Enable (Default: 0x0)

Generates an M66EN interrupt when the PCI Controller is in the Satellite

mode.

Note: This bit must be masked in order to clear an M66EN interrupt since

the M66EN bit of the P2GSTATUS Register itself cannot be cleared.

When the PCI Controller is in the Host mode, M66EN interrupts are

invalid and will not be signaled even if this bit is set to “1”.

1: Generates an interrupt.

0: Does not generate an interrupt.

R/W

20:0

Reseved

⎯

Figure 10.4.19 P2G Interrupt Mask Register

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