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TMPR4937 Datasheet(PDF) 331 Page - Toshiba Semiconductor

Part # TMPR4937
Description  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 Datasheet(HTML) 331 Page - Toshiba Semiconductor

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Chapter 10 PCI Controller
10-73
Bit
Mnemonic
Field Name
Description
Read/Write
4
TCAR
Target
Configuration
Access Ready
Target Configuration Access Ready (Default: 0x0/0x1)
Specifies whether to accept PCI access as a target.
PCI controller receives a target access, when this bit is 1 and
PCISTATUS.E2PDONE bit is 1.
Configuration access from the PCI Bus can be accepted during PCI Boot
up after initialization from EEPROM or after each initialization ends. Please
use the software to set this bit after initialization ends. Retry response to
PCI configuration access is performed until this bit is set.
This bit becomes “1” only when in the PCI Boot Mode and the Satellite
Mode. Operation when this bit is set to “1” then reset to “0” is not defined.
1: Responds to PCI target access.
0: Performs a Retry response to PCI target access.
R/W
3
ICAEN
Initiator
Configuration
Access Enable
Initiator Configuration Access Enable (Default: 0x1)
Controls initiator PCI configuration access using the G2P Configuration
Address Register (G2PCFGADRS) and the G2P Configuration Data
Register (G2PCFGDATA). This is a diagnostic function.
1: Initiator configuration access is possible.
0: Initiator configuration access is not possible.
R/W
2
LCFG
Load
Configuration
Data Register
Load PCI Configuration Data Register (Default: 0x0)
When a software reset is performed on this bit using the Software Reset bit
(PCICFG.SRST) when this bit is already set, data is loaded to the
Configuration Space Register from the Configuration Data 0/1/2/3 Register.
1: Load from the Configuration Data 0/1/2/3 Register.
0: Load from EEPROM.
R/W
1:0
Reserved
⎯
Figure 10.4.41 PCI Controller Configuration Register (3/3)



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