UPSD3422 datasheet(122/293 Pages) STMICROELECTRONICS

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I2C interface

uPSD34xx

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Table 55.

Selection of the SCL Frequency in Master Mode based on fOSC Examples

Note:

These values are beyond the bit rate supported by uPSD34xx.

23.9

I2C interface status register (S1STA)

The S1STA register provides status regarding immediate activity and the current state of

operation on the I2C bus. All bits in this register are read-only except bit 5, INTR, which is

the interrupt flag.

23.9.1

Interrupt conditions

If the I2C interrupt is enabled (EI2C = 1 in SFR named IEA, and EA =1 in SFR named IE),

and the SIOE is initialized, then an interrupt is automatically generated when any one of the

following five events occur:

●

When the SIOE receives an address that matches the contents of the SFR, S1ADR.

Requirements: SIOE is in Slave Mode, and bit AA = 1 in the SFR S1CON.

●

When the SIOE receives General Call address. Requirments: SIOE is in Slave Mode,

bit AA = 1 in the SFR S1CON

●

When a complete data byte has been received or transmitted by the SIOE while in

Master mode. The interrupt will occur even if the Master looses arbitration.

●

When a complete data byte has been received or transmitted by the SIOE while in

selected Slave mode.

●

A STOP condition on the bus has been recognized by the SIOE while in selected Slave

mode.

Selected Slave mode means the device address sent by the Master device at the beginning

of the current data transfer matched the address stored in the S1ADR register.

If the I2C interrupt is not enabled, the MCU may poll the INTR flag in S1STA.

CR2

CR1

CR0

fOSC

Divided

by:

Bit Rate (kHz) @ fOSC

12MHz

fOSC

24MHz

fOSC

36MHz

fOSC

40MHz

fOSC

375

750

X(1)

250

500

750

833

200

400

600

666

120

100

200

300

333

240

100

150

166

480

960

12.5

37.5

1920

6.25

12.5

18.75

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